Shah, Syed Yawar Ali (2000) On synthesis and optimization of floating point units. Masters thesis, Concordia University.
This work describes the effect of architectural/system level design decisions on the performance, of floating point arithmetic units. By modeling with VHDL and using design synthesis techniques, different architectures of floating point adders, multipliers and multiply-accumulate fused units, are compared using different technologies and cell libraries. Some modifications to recent published works have been proposed to minimize the energy delay product with special emphasis on power reduction. A new low power, high performance, transition activity scaled, double data path floating point multiplier has been proposed and its validity is proved by comparing it to a single data path floating point multiplier. A transition activity scaled, triple data path floating point adder has been compared with a high speed, single data path floating point adder using an optimized Leading Zero Anticipatory logic. Three different architectures of floating point multiply-accumulate fused units are evaluated for their desirability for high speed, low power and minimum area. The findings of this work validate different higher level design methodologies of floating point arithmetic units irrespective of the rapidly changing underneath technology.
|Divisions:||Concordia University > Faculty of Engineering and Computer Science > Electrical and Computer Engineering|
|Item Type:||Thesis (Masters)|
|Authors:||Shah, Syed Yawar Ali|
|Pagination:||xii, 158 leaves ; 29 cm.|
|Degree Name:||Theses (M.A.Sc.)|
|Program:||Electrical and Computer Engineering|
|Thesis Supervisor(s):||Al-Khalili, Asim J.|
|Deposited By:||Concordia University Libraries|
|Deposited On:||27 Aug 2009 17:18|
|Last Modified:||04 Nov 2016 19:35|
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