Glavac, Vladimir (2003) A VHDL code generator for Reed-Solomon encoders and decoders. Masters thesis, Concordia University.
Reed-Solomon codes are error correcting codes that are used in many applications such as satellite communications, digital audio tape, and in CDROMs. Such diverse applications call for the use of many different Reed-Solomon codes. The topic of this thesis is the development of a program to produce synthesizable VHDL code for an arbitrary Reed-Solomon encoder or decoder. A novel extension of the Massey-Berlekamp algorithm for solving the key equation is presented. This modified algorithm is a key aspect of the Reed-Solomon decoder designs discussed in this thesis. The details of the design of both RS encoders and decoders are presented in detail. A program written in a high level language was designed so as to generate the VHDL code that corresponds to the algorithms for encoding and decoding. Several encoders and decoders were synthesized for the Xilinx XCV1000 series of field programmable gate arrays (FPGAs). The resulting area and speed metrics are presented for several designs of Reed-Solomon encoders and decoders.
|Divisions:||Concordia University > Faculty of Engineering and Computer Science > Electrical and Computer Engineering|
|Item Type:||Thesis (Masters)|
|Pagination:||xiii, 204 leaves : ill. ; 29 cm.|
|Degree Name:||Theses (M.A.Sc.)|
|Program:||Electrical and Computer Engineering|
|Thesis Supervisor(s):||Soleymani, Mohammad Reza|
|Deposited By:||Concordia University Libraries|
|Deposited On:||27 Aug 2009 17:23|
|Last Modified:||08 Dec 2010 15:23|
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