Qiu, Bing (2003) Diagnosis and yield analysis of a complex interconnection architecture. Masters thesis, Concordia University.
This thesis investigates problems associated with the integration of very large fault-tolerant networks. The focus of the research is on the diagnosis and yield analysis of a complex interconnection architecture. In this thesis, a closed form yield model that takes into account constraints of an architecture has been proposed. It applies to architectures that approximate global redundancy and for which the constraints translate into yield losses. The impact of the constraints on yield can be evaluated by calculating the probability of observing non-tolerable defect patterns and by subtracting these probabilities from yield of arrays with global redundancy. It has been shown that most of the yield losses come from a few patterns comprising small number of defects. According to the characteristics of the analyzed architecture and the nature of defect distributions, different yield models have been derived. With these models, the sensitivity of the yield of the analyzed architecture to variations of the defect density has been investigated. This thesis also proposes regression yield models that can be used to quickly predict the redundancy needed for given array and cell sizes as part of a design flow.
|Divisions:||Concordia University > Faculty of Engineering and Computer Science > Electrical and Computer Engineering|
|Item Type:||Thesis (Masters)|
|Pagination:||xiv, 131 leaves : ill. ; 29 cm.|
|Degree Name:||Theses (M.A.Sc.)|
|Program:||Electrical and Computer Engineering|
|Thesis Supervisor(s):||Wang, Chunyan|
|Deposited By:||Concordia University Libraries|
|Deposited On:||27 Aug 2009 17:23|
|Last Modified:||04 Nov 2016 19:47|
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