Login | Register

Parallel network optimization on a shared memory multiprocessor and application in VLSI layout compaction and wire balancing

Title:

Parallel network optimization on a shared memory multiprocessor and application in VLSI layout compaction and wire balancing

Chalasani, Raghu Prasad (1994) Parallel network optimization on a shared memory multiprocessor and application in VLSI layout compaction and wire balancing. PhD thesis, Concordia University.

[thumbnail of NN90832.pdf]
Preview
Text (application/pdf)
NN90832.pdf
6MB

Abstract

Discusses the design and implementation of 3 parallel algorithms: one algorithm for the transshipment problem, and 2 algorithms for the dual transshipment problem. Also considers an application of these algorithms in solving VLSI layout compaction and wire balancing problems.

Divisions:Concordia University > Gina Cody School of Engineering and Computer Science > Electrical and Computer Engineering
Item Type:Thesis (PhD)
Authors:Chalasani, Raghu Prasad
Pagination:xii, 223 leaves : ill. ; 29 cm.
Institution:Concordia University
Degree Name:Ph. D.
Program:Electrical and Computer Engineering
Date:1994
Thesis Supervisor(s):Thulasiraman, K
Identification Number:QA 76.58 C49 1994
ID Code:3860
Deposited By: Concordia University Library
Deposited On:27 Aug 2009 19:33
Last Modified:13 Jul 2020 19:55
Related URLs:
All items in Spectrum are protected by copyright, with all rights reserved. The use of items is governed by Spectrum's terms of access.

Repository Staff Only: item control page

Downloads per month over past year

Research related to the current document (at the CORE website)
- Research related to the current document (at the CORE website)
Back to top Back to top