Zhang, Shihua (2011) A TLM-RTL Systemverilog-Based Verification Franework for OCP Design. Masters thesis, Concordia University.
|PDF - Accepted Version|
Open Core Protocol (OCP) establishes itself as the only non-proprietary, openly licensed, core-centric protocol that is used to support “plug-and-play” SoC (System-On-Chip) design practices. Designer can reuse OCP-compliance IP cores based on system integration and verification approach in multiple designs without reworking, reducing the development time and cutting down overall design costs.
In this thesis, we develop a reusable verification framework of OCP. Assertion-based verification was chosen in order to enforce the flow. An OCP SystemVerilog monitor which is developed in house is used to verify the OCP SystemC TL1 (Cycle-accurate Level) design. The monitor can also be reused for OCP designs described at different abstraction level and thus dramatically reduce the time needed for OCP functional verification. To increase the functional coverage of OCP models, Cell-based Genetic Algorithm (CGA) with random number generators based on different probability distribution functions is provided on OCP TL1 models for generating and evolving the OCP transactions. Furthermore, SystemC Verification Library (SCV) is employed as pure random number generator to compare with the proposed CGA. The experiments show that some probability distributions have more effect on the coverage than others. The best population of the CGA can be reused on OCP RTL models to reduce the verification time.
|Divisions:||Concordia University > Faculty of Engineering and Computer Science > Electrical and Computer Engineering|
|Item Type:||Thesis (Masters)|
|Degree Name:||M.A. Sc.|
|Program:||Electrical and Computer Engineering|
|Date:||14 April 2011|
|Thesis Supervisor(s):||Ait Mohamed, Otmane|
|Deposited By:||SHI HUA ZHANG|
|Deposited On:||08 Jun 2011 16:00|
|Last Modified:||04 Jan 2012 15:12|
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