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Binary operation procedure for thinning process and its VLSI implementation in a pixel array circuit

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Binary operation procedure for thinning process and its VLSI implementation in a pixel array circuit

Wu, Kuo-Ting (2005) Binary operation procedure for thinning process and its VLSI implementation in a pixel array circuit. Masters thesis, Concordia University.

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Abstract

In this thesis, the design of a pixel array circuit for thinning process is presented. The research efforts of this work are on the two aspects: the processing algorithm and the circuit design. In the aspect of algorithm, a new thinning process is designed aiming at an easy implementation in a VLSI pixel array circuit. The computation is made in parallel and with a small number of direct data transfers among the neighboring pixels, which leads to a fast processing and fewer metal connections in the circuit. The effectiveness of the algorithm has been proved in the simulation. The other aspect of this work is the design of a pixel array circuit implementing the image acquisition and the proposed thinning process

Divisions:Concordia University > Faculty of Engineering and Computer Science > Electrical and Computer Engineering
Item Type:Thesis (Masters)
Authors:Wu, Kuo-Ting
Pagination:viii, 69 leaves : ill. ; 29 cm.
Institution:Concordia University
Degree Name:M.A. Sc.
Program:Electrical and Computer Engineering
Date:2005
Thesis Supervisor(s):Wang, C
ID Code:8231
Deposited By:Concordia University Libraries
Deposited On:18 Aug 2011 14:19
Last Modified:18 Aug 2011 14:19
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