Breadcrumb

 
 

Architecture and circuit techniques for a 2 GHz advanced high-speed bus SoC interconnect infrastructure

Title:

Architecture and circuit techniques for a 2 GHz advanced high-speed bus SoC interconnect infrastructure

Landry, Alexandre (2005) Architecture and circuit techniques for a 2 GHz advanced high-speed bus SoC interconnect infrastructure. Masters thesis, Concordia University.

[img]
Preview
PDF - Accepted Version
4Mb

Abstract

A key issue with high performance SoC platforms is how to interconnect their modules to effectively transfer large amounts of data in real-time. Today's most practical communication infrastructures are bus-based due to the small number of processing elements residing on a silicon die. Since the bandwidth of a shared bus goes down with the number of bus masters, hierarchical structures are used to parallelize transfers and to obtain a higher throughput. Hence, a novel shared memory SoC communication infrastructure based on the Advanced High-Speed Bus (AHB) is defined in this thesis. The objective of this dissertation is to explore various avenues to design a bus operating with a clock in excess of 2 GHz when targeting a 0.18 om CMOS process. As a first iteration, the fastest circuit techniques are reviewed so as to traverse the learning curve that a designer must experiment with very high-speed designs. To enhance the understanding of high-speed circuit styles, the main cores of an AHB are implemented from a novel, and aggressive, true-single-phase-clocking (TSPC) circuit style. The 2 GHz AHB arbiter has been laid out to prove the performance of the circuit techniques explored with the full-custom SoC infrastructure. In addition, an innovative 2 GHz pipelined memory has been created to respond to the hard IP requirements.

Divisions:Concordia University > Faculty of Engineering and Computer Science > Electrical and Computer Engineering
Item Type:Thesis (Masters)
Authors:Landry, Alexandre
Pagination:xiii, 103 leaves : ill. ; 29 cm.
Institution:Concordia University
Degree Name:M.A. Sc.
Program:Electrical and Computer Engineering
Date:2005
Thesis Supervisor(s):Nekili, Mohamed
ID Code:8313
Deposited By:Concordia University Libraries
Deposited On:18 Aug 2011 14:21
Last Modified:18 Aug 2011 14:21
Related URLs:
All items in Spectrum are protected by copyright, with all rights reserved. The use of items is governed by Spectrum's terms of access.

Repository Staff Only: item control page

Document Downloads

More statistics for this item...

Concordia University - Footer