Sajjadi, Seyed-Abbas (2005) A computer-aided design tool for analog integrated circuit building blocks realization. Masters thesis, Concordia University.
MR04391.pdf - Accepted Version
With the advent of submicron CMOS process technologies, application of current-voltage model equation, which is good for long channel devices, is becoming futile. Shortage of analog integrated circuits design automation tools results in relying on engineering experience and time-consuming trial and error simulation runs to design an analog integrated circuit (IC). Many designers are faced with the large design time devoted to the design of analog circuits in comparing with digital counterparts in mixed-signal IC designs. The research presented in this thesis aims to improve the efficiency of analog IC design process with a new design methodology and computer-aided design program for automating the realization of analog IC building blocks. The new design methodology is based on small-signal analysis, and DC simulation of NMOS and PMOS transistors which is predicted by sophisticated circuit analysis program i.e. HSPICE. The CAD tool is intended to be a design assistant and comprises of a number of modules including setup, single stage amplifier design, current source/mirror design, voltage divider design, differential amplifier design, operational amplifier and operational transconductance amplifier design modules. To demonstrate the usefulness and reliability of the new methodology and the tool, some design examples are presented. This thesis also studies the analog design automation methods and tools that have been reported in the literature.
|Divisions:||Concordia University > Faculty of Engineering and Computer Science > Electrical and Computer Engineering|
|Item Type:||Thesis (Masters)|
|Pagination:||xiv, 135 leaves : ill. ; 29 cm.|
|Degree Name:||M.A. Sc.|
|Program:||Electrical and Computer Engineering|
|Thesis Supervisor(s):||Raut, Rabin and Sinha, P|
|Deposited By:||Concordia University Libraries|
|Deposited On:||18 Aug 2011 18:25|
|Last Modified:||05 Nov 2016 00:21|
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