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New motion estimation techniques and their SIMD implementations for video coding

Title:

New motion estimation techniques and their SIMD implementations for video coding

Duanmu, Chunjiang (2005) New motion estimation techniques and their SIMD implementations for video coding. PhD thesis, Concordia University.

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Abstract

Compression of video signals is of great importance to modern multi-media systems. In order to achieve efficient data compression, block motion estimation is generally employed to remove temporal redundancies inherent in video signals and thus, it is a crucial component of international video coding standards. This thesis aims at developing techniques to reduce the computational complexity of a given block motion estimation algorithm without sacrificing its accuracy, to utilize the single instruction multiple data (SIMD) technique to accelerate a block motion estimation process, and to develop a new fast block motion estimation algorithm suitable for implementation using SIMD architecture. A method to detect blocks that are stationary between successive frames, is proposed. In this method, when a block is judged as stationary, the search process for such a block is skipped in the block motion estimation process. The statistical characteristics of the video sequence are utilized in deciding as to which blocks are stationary. Simulation studies are carried out showing that this method reduces the computational complexity of the various block motion estimation algorithms without sacrificing the accuracy of the original algorithm. A vector-based fast block motion estimation algorithm, suitable for implementation on an SIMD architecture, is proposed. This algorithm maintains the accuracy and coding efficiency of the full-search algorithm, but the complexity is only a very small fraction of that of the full-search algorithm. It is also shown that by implementing the proposed algorithm on an SIMD architecture, the execution time of the algorithm can be further reduced by about 74%. The concept of an eight-bit partial sum is introduced so as to take advantage of the byte-type data parallelism in the existing SIMD architectures. A method of employing these partial sums to speedup a given block motion estimation process is proposed. The notion of the eight-bit partial sums is extended to the four-level case and it is shown that there are fifteen possible methods of utilizing these multi-level partial sums to accelerate block motion estimation algorithms. It is shown that any of these fifteen methods can accelerate a given block motion estimation algorithm without any loss of accuracy. The full-search algorithm is used to determine as to which one of these fifteen methods would provide the lowest computational complexity in order for it to be chosen to accelerate the various motion estimation algorithms. Simulation studies have been conducted and the results show that the proposed scheme is capable of providing a substantial speedup for the various existing motion estimation algorithms without any loss of accuracy.

Divisions:Concordia University > Faculty of Engineering and Computer Science > Electrical and Computer Engineering
Item Type:Thesis (PhD)
Authors:Duanmu, Chunjiang
Pagination:xxi, 135 leaves : ill. ; 29 cm.
Institution:Concordia University
Degree Name:Ph. D.
Program:Electrical and Computer Engineering
Date:2005
Thesis Supervisor(s):Ahmad, M. Omair
ID Code:8564
Deposited By:Concordia University Libraries
Deposited On:18 Aug 2011 14:28
Last Modified:18 Aug 2011 15:23
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