Moinudeen, Haja (2006) Design for verification of a PCI-X bus model. Masters thesis, Concordia University.
|PDF - Accepted Version|
The importance of re-usable Intellectual Properties (IPs) cores and the system-level design languages have been increasing due to the growing complexity of today's System-on-Chip (SoC) and the need for rapid prototyping. In this respect, the SystemC language is becoming an industrial standard to be used as a modeling language for SoCs at the system level. Nevertheless, it is of paramount importance to have SystemC IPs in particular bus standards in order to facilitate SoC designs using SystemC. PCI-X is the fastest and latest extension of PCI (Peripheral Component Interconnect) technologies that is backward compatible to previous PCI versions. It plays a crucial role in today's SoC since it helps to connect various on chip IPs. In this thesis, we provide a design for verification approach for the PCI-X bus. We use different modeling levels, namely UML, AsmL and SystemC to design and verify the PCI-X. From informal specifications, we first represent the PCI-X model in UML where a precise capture of design requirements is possible.
|Divisions:||Concordia University > Faculty of Engineering and Computer Science > Electrical and Computer Engineering|
|Item Type:||Thesis (Masters)|
|Pagination:||xv, 94 leaves ; 29 cm.|
|Degree Name:||Theses (M.A. Sc.)|
|Program:||Electrical and Computer Engineering|
|Thesis Supervisor(s):||Tahar, Sofiène|
|Deposited By:||Concordia University Libraries|
|Deposited On:||18 Aug 2011 14:40|
|Last Modified:||18 Aug 2011 14:40|
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