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Verification and validation in systems engineering : application to UML 2.0 activity and class diagrams

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Verification and validation in systems engineering : application to UML 2.0 activity and class diagrams

Alawneh, Lu'ay (2006) Verification and validation in systems engineering : application to UML 2.0 activity and class diagrams. Masters thesis, Concordia University.

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Abstract

The increasing complexity of industrial systems requires more efforts to be invested in the process of system verification and validation. The quality of such systems depends on the different types of techniques that are used to verify and ensure their correct functionality. The cost of maintaining systems in the latter phases of development is usually very high and may lead in most of the cases to inefficient solutions. Therefore, checking the correctness and validity of systems early in the design phase is greatly desirable. Different verification and validation techniques such as those involving testing and simulation are helpful and useful but may lack in many cases the desired level of rigor and completeness. Moreover, these conventional techniques are generally costly, laborious and time consuming. Conversely, using formal techniques, such as model-checking and program analysis along with design metrics complementary to the conventional verification techniques provides an elevated level of confidence since they are based on theoretical foundations. Systems Engineering is an interdisciplinary approach that aims to enable the successful realization and deployment of complex systems. Many modeling languages emerged in the systems engineering arena in order to provide the means for capturing and modeling of system's specifications and requirements. The most prominent languages are Unified Modeling Language (UML) 2.0 and Systems Modeling Languages (SysML). Formal verification and software engineering techniques can be applied in order to assess the correctness of different diagrams belonging to the aforementioned modeling languages. This research work presents a unified paradigm for the verification and validation of software and systems engineering design models expressed in UML 2.0 or SysML. The proposed paradigm relies on an established synergy between three salient approaches, which are model-checking, program analysis, and software engineering techniques

Divisions:Concordia University > Faculty of Engineering and Computer Science > Electrical and Computer Engineering
Item Type:Thesis (Masters)
Authors:Alawneh, Lu'ay
Pagination:ix, 95 leaves : ill. ; 29 cm.
Institution:Concordia University
Degree Name:M.A. Sc.
Program:Electrical and Computer Engineering
Date:2006
Thesis Supervisor(s):Assi, Chadi
ID Code:9209
Deposited By:Concordia University Libraries
Deposited On:18 Aug 2011 14:46
Last Modified:29 Nov 2011 13:33
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