Kafashe Panjeh Shahi, Payam (2006) Verification and validation techniques in systems engineering : application to state-chart diagrams. Masters thesis, Concordia University.
- Accepted Version
Verification and validation have become very important steps in systems engineering. This is due to the increasing complexity of nowadays systems. Verification and validation aims at detecting flaws early in the design process and/or to verify/validate design models of systems. The state of the art techniques in this field are mainly based on simulation and extensive testing. In this thesis, we propose a new paradigm for verification and validation in systems engineering. It is based on an established synergy between program analysis, software engineering techniques and automatic verification. To illustrate this paradigm, we present a technique for the verification/validation of state-chart diagrams in UML/SysML modeling languages.
|Divisions:||Concordia University > Faculty of Engineering and Computer Science > Electrical and Computer Engineering|
|Item Type:||Thesis (Masters)|
|Authors:||Kafashe Panjeh Shahi, Payam|
|Pagination:||xii, 119 leaves : ill. ; 29 cm.|
|Degree Name:||M.A. Sc.|
|Program:||Electrical and Computer Engineering|
|Thesis Supervisor(s):||Debbabi, Mourad|
|Deposited By:||Concordia University Libraries|
|Deposited On:||18 Aug 2011 18:47|
|Last Modified:||29 Nov 2011 21:25|
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