Pillai, Rajan V. K (1999) On low power floating point data path architectures. PhD thesis, Concordia University.
This work targets development of higher level design methodologies for the implementation of low power floating point units--adders, multipliers and multiply-accumulators. Philosophically, higher level design starts with the characterization of the behavior of the system under consideration. In this work, the design philosophy of floating point adders and multiply accumulators is centered around the significand alignment driven power behavior of these units. Transition activity scaling of these units, taking into account the behavior of exponents, provides a viable high level approach for the design of these units. The exponent behavior based design partition also allows simplification of data paths, so that the speed performance of these units are enhanced. With transition activity scaling, the switching activity of the floating point units is mapped to a limited subset of the hardware real estate, so that the time averaged power consumption of these units is optimal. In order to validate the design methodology, high level power/delay models that reflect the architecture of the functional units are developed. The behavior of the architectures is validated through simulations. Instrumented digital filter programs that emulate the multiply-accumulate segment of DSP systems form the core of our experimental platform.
|Divisions:||Concordia University > Faculty of Engineering and Computer Science > Electrical and Computer Engineering|
|Item Type:||Thesis (PhD)|
|Authors:||Pillai, Rajan V. K|
|Pagination:||xi, 209 leaves : ill. ; 29 cm.|
|Degree Name:||Theses (Ph.D.)|
|Program:||Electrical and Computer Engineering|
|Thesis Supervisor(s):||Al-Khalili, Asim J|
|Deposited By:||Concordia University Libraries|
|Deposited On:||27 Aug 2009 17:15|
|Last Modified:||04 Nov 2016 18:10|
Repository Staff Only: item control page