Breadcrumb

 
 

A Framework for Noise Analysis and Verification of Analog Circuits

Title:

A Framework for Noise Analysis and Verification of Analog Circuits

Narayanan, Rajeev (2012) A Framework for Noise Analysis and Verification of Analog Circuits. PhD thesis, Concordia University.

This is the latest version of this item.

[img]
Preview
PDF - Accepted Version
2220Kb

Abstract

Analog circuit design and verification face significant challenges due to circuit complexity and short market windows. In particular, the influence of technology parameters on circuits, noise modeling and verification still remain a priority for many applications. Noise could
be due to unwanted interaction between the various circuit blocks or it could be inherited from the circuit elements. Current industrial designs rely heavily on simulation techniques, but ensuring the correctness of such designs under all circumstances usually becomes impractically
expensive. In this PhD thesis, we propose a methodology for modeling and verification of analog designs in the presence of noise and process variation using run-time verification methods. Verification based on run-time techniques employs logical or statistical monitors to check if an execution (simulation) of the design model violates the design
specifications (properties). In order to study the random behavior of noise, we propose an approach based on modeling the designs using stochastic differential equations (SDE) in the time domain. Then, we define assertion and statistical verification methods in a MATLAB SDE simulation framework for monitoring properties of interest in order to detect errors.
In order to overcome some of the drawbacks associated with monitoring techniques, we
define a pattern matching based verification method for qualitative estimation of the simulation
traces. We illustrate the efficiency of the proposed methods on different benchmark
circuits.

Divisions:Concordia University > Faculty of Engineering and Computer Science > Electrical and Computer Engineering
Item Type:Thesis (PhD)
Authors:Narayanan, Rajeev
Institution:Concordia University
Degree Name:Ph. D.
Program:Electrical and Computer Engineering
Date:16 April 2012
ID Code:973941
Deposited By:RAJEEV NARAYANAN
Deposited On:20 Jun 2012 15:30
Last Modified:15 Nov 2012 16:36

Available Versions of this Item

  • A Framework for Noise Analysis and Verification of Analog Circuits. (deposited 20 Jun 2012 15:30) [Currently Displayed]
All items in Spectrum are protected by copyright, with all rights reserved. The use of items is governed by Spectrum's terms of access.

Repository Staff Only: item control page

Document Downloads

More statistics for this item...

Concordia University - Footer