Narayanan, Rajeev (2012) A Framework for Noise Analysis and Verification of Analog Circuits. PhD thesis, Concordia University.
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Thesis_Final.pdf - Accepted Version
Analog circuit design and verification face significant challenges due to circuit complexity and short market windows. In particular, the influence of technology parameters on circuits, noise modeling and verification still remain a priority for many applications. Noise could
be due to unwanted interaction between the various circuit blocks or it could be inherited from the circuit elements. Current industrial designs rely heavily on simulation techniques, but ensuring the correctness of such designs under all circumstances usually becomes impractically
expensive. In this PhD thesis, we propose a methodology for modeling and verification of analog designs in the presence of noise and process variation using run-time verification methods. Verification based on run-time techniques employs logical or statistical monitors to check if an execution (simulation) of the design model violates the design
specifications (properties). In order to study the random behavior of noise, we propose an approach based on modeling the designs using stochastic differential equations (SDE) in the time domain. Then, we define assertion and statistical verification methods in a MATLAB SDE simulation framework for monitoring properties of interest in order to detect errors.
In order to overcome some of the drawbacks associated with monitoring techniques, we
define a pattern matching based verification method for qualitative estimation of the simulation
traces. We illustrate the efficiency of the proposed methods on different benchmark
|Divisions:||Concordia University > Faculty of Engineering and Computer Science > Electrical and Computer Engineering|
|Item Type:||Thesis (PhD)|
|Degree Name:||Ph. D.|
|Program:||Electrical and Computer Engineering|
|Date:||16 April 2012|
|Deposited By:||RAJEEV NARAYANAN|
|Deposited On:||20 Jun 2012 19:30|
|Last Modified:||05 Nov 2016 02:04|
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