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Optimum partitioning of globally asynchronous locally synchronous processor arrays


Optimum partitioning of globally asynchronous locally synchronous processor arrays

Upadhyay, Adhir (2004) Optimum partitioning of globally asynchronous locally synchronous processor arrays. Masters thesis, Concordia University.

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MQ91130.pdf - Accepted Version


Globally Asynchronous Locally Synchronous design style has evolved as a solution to increasing problems of distributing clocks at high frequency and with lower power consumption in DSM technologies. In GALS designs, partitioning a system into more locally synchronous sub-blocks reduces the size of each sub-block and allows higher clock frequency. Also, smaller sub-blocks reduce the capacitance in the clock networks because they need less H-tree levels. However, this implies a large number of sub-blocks, which increases the asynchronous power overhead. The thesis considers a 16 x 16 array of identical processors to evaluate GALS tradeoffs with different partitioning scenarios. Three different configurations of the array have been studied. This is, to our knowledge, the first work to propose closed form models for the optimum number of sub-blocks that accomplish minimum power for GALS design with passive clock distribution networks. Experimental results verify the effectiveness of the models. The potential increase in the clock frequency with partitioning and its effect on total power consumption has also been investigated for one of the array configurations. For large VLSI designs, inserting repeaters in the clock network is an alternative to boost the clock frequency that often is limited by the interconnect bandwidth. The thesis also investigates the GALS tradeoffs for an array with active clock networks. An algorithm has been proposed to evaluate the optimum partitioning in this case. The Delay-Insensitive (DI) asynchronous protocols offer a promising solution to the timing closure problem with long global interconnects in synchronous designs. A novel asynchronous wrapper using 1-of-4 DI protocol has been introduced. Simulation results show that the scheme achieves 66% higher throughput than previous designs.

Divisions:Concordia University > Gina Cody School of Engineering and Computer Science > Electrical and Computer Engineering
Item Type:Thesis (Masters)
Authors:Upadhyay, Adhir
Pagination:v, 101 leaves : ill. ; 29 cm.
Institution:Concordia University
Degree Name:M.A. Sc.
Program:Electrical and Computer Engineering
Thesis Supervisor(s):Nekili, M
Identification Number:TK 7888.3 U63 2004
ID Code:7884
Deposited By: Concordia University Library
Deposited On:18 Aug 2011 18:09
Last Modified:13 Jul 2020 20:02
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