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Automatic Generation of Transducer Models for Bus-Based MPSoC Design


Automatic Generation of Transducer Models for Bus-Based MPSoC Design

Cho, Hansu, Yu, Lochi and Abdi, Samar (2013) Automatic Generation of Transducer Models for Bus-Based MPSoC Design. IEEE Transactions on Computers, 62 (2). pp. 211-224. ISSN 0018-9340

Text (application/pdf)
abdi2012.pdf - Accepted Version

Official URL: http://dx.doi.org/10.1109/TC.2012.157


This paper presents methods for automatic generation of models of Transducer, a highly flexible communication module for interfacing Multiprocessor System-on-Chip (MPSoC) components. We describe the transducer architecture, comprising the bus interface, high-level communication controllers and buffer management blocks. The well-defined architecture of the transducer enables automatic generation of its Transaction-level and Register-transfer level (RTL) models. Moreover, the simple interface of the transducer provides for a well-defined software interface, making it easy to update the software after changes in MPSoC platform. Our experimental results show that MPSoC design for industrial-size applications, such as MP3 decoder and JPEG encoder, greatly benefits from automatic generation of transducer models. We found productivity gains of 9-23× due to significant savings in modeling effort. On the quality axis, we show that MPSoC communication design using automatically generated transducers has very little overhead in communication delay over a fully connected point-to-point communication architecture. Finally, we show that our automatically generated TLMs greatly reduce the system-level modeling time and provide a fast executable model for early functional validation.

Divisions:Concordia University > Gina Cody School of Engineering and Computer Science > Electrical and Computer Engineering
Item Type:Article
Authors:Cho, Hansu and Yu, Lochi and Abdi, Samar
Journal or Publication:IEEE Transactions on Computers
Digital Object Identifier (DOI):10.1109/TC.2012.157
Keywords:Abstracts , Computer architecture , Protocols , Software , Time domain analysis , Time varying systems , Transducers, Multiprocessor System-on-Chip Design , System-level modeling , communication architecture
ID Code:975144
Deposited On:18 Jan 2013 18:24
Last Modified:18 Jan 2018 17:39


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