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Exploiting Bounds Optimization for the Semi-formal Verification of Analog Circuits


Exploiting Bounds Optimization for the Semi-formal Verification of Analog Circuits

Lahiouel, Ons, Aridhi, Henda, Zaki, Mohamed H. and Tahar, Sofiène (2017) Exploiting Bounds Optimization for the Semi-formal Verification of Analog Circuits. Integration, the VLSI Journal . ISSN 01679260 (In Press)

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Exploiting-Bounds-Optimization-for-the-Semi-formal-Verification-of-Analog-Circuits_2017_Integration-the-VLSI-Journal.pdf - Accepted Version
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Official URL: http://dx.doi.org/10.1016/j.vlsi.2017.06.008


This paper proposes a semi-formal methodology for modeling and verification of analog circuits behavioral properties using multivariate optimization techniques. Analog circuit differential models are automatically extracted and their qualitative behavior is computed for interval-valued parameters, inputs and initial conditions. The method has the advantage of guaranteeing the rough enclosure of any possible dynamical behavior of analog circuits. The circuit behavioral properties are then verified on the generated transient response bounds. Experimental results show that the resulting state variable envelopes can be effectively employed for a sound verification of analog circuit properties, in an acceptable run-time.

Divisions:Concordia University > Gina Cody School of Engineering and Computer Science > Electrical and Computer Engineering
Item Type:Article
Authors:Lahiouel, Ons and Aridhi, Henda and Zaki, Mohamed H. and Tahar, Sofiène
Journal or Publication:Integration, the VLSI Journal
Date:23 June 2017
Digital Object Identifier (DOI):10.1016/j.vlsi.2017.06.008
Keywords:Analog Circuits; Global Optimization; Verification; Qualitative Simulation
ID Code:982648
Deposited On:28 Jun 2017 14:46
Last Modified:01 Jun 2018 00:00


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