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Validation and Enhancement of Two-Level Inverter Models for Very Low Time-Step Real-Time Applications


Validation and Enhancement of Two-Level Inverter Models for Very Low Time-Step Real-Time Applications

Abdalla, Ahmed K (2017) Validation and Enhancement of Two-Level Inverter Models for Very Low Time-Step Real-Time Applications. Masters thesis, Concordia University.

Text (application/pdf)
Abdalla_MASc_S2018.pdf - Accepted Version


Very low time-step real-time simulations are highly needed when simulating power converters to capture the fast transients caused by the switching devices of the converter. With very low time-steps, it is possible to represent fast transitions precisely and enhance simulation accuracy. FPGA-based solutions are mandatory to carry out very low time-step simulations. However, the complexity of FPGA programming makes such simulations undesirable for many users who might lack the required programming skills. A solver called eHS developed by OPAL RT establishes itself as a solution for this problem. It is designed to shadow the complexity of FPGA programming by automatically generating the code of the converter for the user.
FPGA-based low time-step real-time simulations, however, impose restrictions on the switch model that can be used to represent the converter. The switch model should be as simple as possible yet provides a good representation of a switch. It should inherit minimum computational efforts such that the requirements of low time-step simulations are satisfied. Several switch models offered in the literature are reviewed and discussed. Afterwards, a criterion to compare between these models is set and followed to select the most suitable one among the considered alternatives.
The main objective of this research work is to validate the converter models used in real-time simulations. This includes the converter, composed of the chosen switch model, programmed on the FPGA using the eHS solver. This entire model will be validated in offline and in real-time against a physical setup. More specifically, a new test plan to validate the converter model against an experimental setup is proposed and tested. The results of the converter simulated at a very low time-step on an FPGA through the eHS solver are compared to results from a real converter. Furthermore, the performance of the converter is tested in various operating conditions including unbalanced load and faulty situations. Based on the results of the offline and real-time validation, several recommendations on system improvement are proposed in the last chapter.

Divisions:Concordia University > Gina Cody School of Engineering and Computer Science > Electrical and Computer Engineering
Item Type:Thesis (Masters)
Authors:Abdalla, Ahmed K
Institution:Concordia University
Degree Name:M.A. Sc.
Program:Electrical and Computer Engineering
Date:27 November 2017
Thesis Supervisor(s):Rathore, Akshay and Nasrallah, Danielle
ID Code:983382
Deposited By: Ahmed Kotb Abdalla
Deposited On:11 Jun 2018 02:19
Last Modified:11 Jun 2018 02:19
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