Login | Register

Mixed-Signal Implementation of Low-Density Parity-Check Decoder

Title:

Mixed-Signal Implementation of Low-Density Parity-Check Decoder

Basak, Sanjoy (2017) Mixed-Signal Implementation of Low-Density Parity-Check Decoder. Masters thesis, Concordia University.

[img]
Preview
Archive (application/pdf)
Basak_MASc_S2018.pdf - Accepted Version
Available under License Spectrum Terms of Access.
5MB

Abstract

The receiver side of many communication systems incorporates an error-correction decoder to achieve good bit-error rate (BER) performance. While good BER is a metric of reliable communication, high throughput and energy-efficiency are also desired. Low-density parity-check (LDPC) decoders are able to perform well in term of these metrics. In this thesis, the Modified Differential Decoding Binary Message Passing (MDD-BMP) algorithm of LDPC codes has been chosen to implement in mixed-signal domain. The goal of this research is to achieve energy-efficiency in LDPC decoding while maintaining high-throughput in an implemented design of reasonable effective area.
The re-design of some digital parts of the LDPC decoder in analog domain is expected to offer energy-efficiency and high throughput. However, these benefits come at a cost of analog impairments, such as, different random mismatch between similar inverters arising from process variation during fabrication. The comparative contribution of these impairments on the BER performance of the decoder has been investigated. During the design of the decoder, an on-chip calibration scheme has been arranged and global routing of the tuning signals has been maintained to address these random mismatches. Furthermore, modulation of the decoding speed by off-chip tuning has been made possible. For the purpose of high-speed testing of the decoding process, enough on-chip memory has been placed to store 10 codewords and feed them to the decoder through a binary-weighted capacitor-based digital to analog converter. Design and placement of analog MUXes enable us to debug sensitive analog nodes inside the decoder from off-chip. Finally, the full process of the physical design of the decoder in TSMC 65nm has been almost fully automated in Cadence SKILL code. Over 100 simulations including parasitic capacitance of long wires in physical design yield an average decoding speed of approximately 2.04 ns in moderate speed mode, therefore, providing a high throughput of 134 Gb/s. Taking into account the average current drawn by the circuits during both the pre-charge phase and the decoding phase, the calculated average energy per bit consumed by the decoder is 1.267 pJ/bit.

Divisions:Concordia University > Gina Cody School of Engineering and Computer Science > Electrical and Computer Engineering
Item Type:Thesis (Masters)
Authors:Basak, Sanjoy
Institution:Concordia University
Degree Name:M.A. Sc.
Program:Electrical and Computer Engineering
Date:12 December 2017
Thesis Supervisor(s):Cowan, Glenn and Gross, Warren J.
Keywords:Low-density Parity-check, Mixed-signal decoder, Analog VLSI
ID Code:983409
Deposited By: Sanjoy Basak
Deposited On:11 Jun 2018 02:59
Last Modified:11 Jun 2018 02:59

References:

[1] C. E. Shannon, “A mathematical theory of communication,” Bell Syst. Tech. J., vol. 27, pp. 379−423, 623−656, 1948.
[2] D. J. C. MacKay and R. M. Neal, “Near Shannon Limit performance of low density parity check codes,” Electronics Letters, vol. 32, no. 18, pp. 1645−1646, 1996.
[3] T. Richardson and R. Urbanke, “The capacity of low-density parity-check codes under message-passing decoding,” IEEE Transactions on Information Theory, vol. 47, no. 2, pp. 599-618, Feb. 2001.
[4] Y. Kou, S. Lin, and M. Fossorier, “Low-density parity-check codes based on finite geometries: A rediscovery and new results,” IEEE Transactions on Information Theory, vol. 47, no. 7, pp. 2711−2736, Nov. 2001.
[5] R. Gallager, Low-Density Parity-Check Codes. Cambridge, MA, USA: MIT Press, 1963.
[6] D. J. C. Mackay, “Good error-correcting codes based on very sparse matrices,” IEEE Transactions on Information Theory, vol. 45, no. 2, March 1999.
[7] F. R. Kschischang, B. J. Frey, and H. A. Loeliger, “Factor graphs and the sum-product algorithm,” IEEE Transactions on Information Theory, vol. 47, pp. 498-519, Feb. 2001.
[8] S. Hemati and A. Banihashemi, “Dynamics and performance analysis of analog iterative decoding for low-density parity-check (LDPC) codes,” IEEE Transactions on Communications, vol. 54, no. 1, Jan. 2006.
[9] J. M. Ortega and W. C. Rheinboldt, Iterative Solution of Nonlinear Equations in Several Variables. New York: Academic, 1970.
[10] C. T. Kelley, Iterative Methods for Linear and Nonlinear Equations. Philadelphia, PA: SIAM, 1995.
[11] H. Xiao, S. Tolouei, and A. H. Banihashemi, “Successive relaxation for decoding of LDPC codes,” 24th Queen’s Biennial Symposium on Communication, Kingston, Ontario, June 2008.
[12] N. Mobini, A. Banihashemi, and S. Hemati, “ A differential binary message passing LDPC decoder,” IEEE Transactions on Communication, vol. 57, no. 9, pp. 2518-2523, Sep. 2009.
[13] K. Cushon, S. Hemati, C. Leroux, S. Mannor, and W. J. Gross, “High-throughput energy-efficient LDPC decoders using differential binary message passing,” IEEE Transactions on Signal Processing, vol. 62, no. 3, pp. 619-631, February 2014.
[14] R. M. Tanner, “A recursive approach to low complexity codes,” IEEE Transactions on Information Theory, vol. IT-27, pp. 533-547, Sept. 1981.
[15] L. Bazzi, T. Richardson, and R. Urbanke, “Exact thresholds and optimal codes for the binary-symmetric channel and Gallager’s decoding algorithm A,” IEEE Transactions on Information Theory, vol. 50, no. 9, pp. 2010−2021, Sept. 2004.
[16] N. Miladinovic and M. Fossorier, “Improved bit-flipping decoding of low-density parity-check codes,” IEEE Transactions on Information Theory, vol. 51, no. 4, pp. 1594-1606, Apr. 2005.
[17] P. Zarrinkhat and A. Banihashemi, “Threshold values and convergence properties of majority-based algorithms for decoding regular low-density parity-check codes,” IEEE Transactions on Communication, vol. 52, no. 12, pp. 2087-2097, Dec. 2004.
[18] G. Cowan, K. Cushon, and W. Gross, “Mixed-signal implementation of differential decoding using binary message passing algorithms,” IEEE 26th International Conference on Application-specific Systems, Architectures and Processors, Toronto, July 27-29, 2015.
[19] S. Hemati, A. H. Banihashemi, and C. Plett, “A 0.18-um CMOS analog min-sum iterative decoder for a (32,8) low-density parity-check (LDPC) code,” IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2531−2540, 2006.
[20] A. Darabiha, A. C. Carusone, and F. R. Kschischang, “Power reduction techniques for LDPC decoders,” IEEE Journal of Solid-State Circuits, vol. 43, no. 8, pp. 1835−1845, August 2008.
[21] C. Chen, Y. Lin, H. Chang, and C. Lee, “A 2.37-Gb/s 284.8 mW rate-compatible (491,3,6) LDPC-CC decoder,” IEEE Journal of Solid-State Circuit, vol. 47, no. 4, pp. 817−831, 2012.
[22] A. R. Abolfazli, Y. R. Shayan, G. E. R. Cowan, “750Mb/s 17pJ/b 90nm CMOS (120,75) TS-LDPC min-sum based analog decoder,” IEEE Asian Solid-State Circuits Conference, Singapore, Nov. 11-13, 2013.
[23] C. Cheng, J. Yang, H. Lee, C. Yang, Y. Ueng, “A fully-parallel LDPC decoder architecture using probabilistic min-sum algorithm for high-throughput applications,” IEEE Transactions on Circuits and Systems I, vol. 61, no. 9, pp. 2738−2746, April 2014.
[24] Y. Toriyama and D. Markovic, “A 2.267 Gbps, 93.7 pJ/b non-binary LDPC decoder for storage applications,” IEEE Symposium on VLSI circuits, Kyoto, June 5-8, 2017.
All items in Spectrum are protected by copyright, with all rights reserved. The use of items is governed by Spectrum's terms of access.

Repository Staff Only: item control page

Downloads per month over past year

Back to top Back to top