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An Efficient Hardware Implementation of LDPC Decoder

Title:

An Efficient Hardware Implementation of LDPC Decoder

Yasoubi, Monazzahalsadat (2020) An Efficient Hardware Implementation of LDPC Decoder. Masters thesis, Concordia University.

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Abstract

Reliable communication over noisy channel is an old but still challenging issues for communication engineers. Low density parity check codes (LDPC) are linear block codes proposed by Robert G. Gallager in 1960. LDPC codes have lesser complexity compared to Turbo-codes. In most recent wireless communication standard, LDPC is used as one of the most popular forward error correction (FEC) codes due to their excellent error-correcting capability. In this thesis we focus on hardware implementation of the LDPC used in Digital Video Broadcasting - Satellite - Second Generation (DVB-S2) standard ratified in 2005. In architecture design of LDPC decoder, because of the structure of DVB-S2, a memory mapping scheme is used that allows 360 functional units implement simultaneously. The functional units are optimized to reduce hardware resource utilization on an FPGA. A novel design of Range addressable look up table (RALUT) for hyperbolic tangent function is proposed that simplifies the LDPC decoding algorithm while the performance remains the same. Commonly, RALUTs are uniformly distributed on input, however, in our proposed method, instead of representing the LUT input uniformly, we use a non-uniform scale assigning more values to those near zero. Zynq XC7Z030, a family of FPGA’s, is used for Evaluation of the complexity of the proposed design. Synthesizes result show the speed increase due to use of LUT method, however, LUT demand more memory. Thus, we decrease the usage of resource by applying RALUT method.

Divisions:Concordia University > Gina Cody School of Engineering and Computer Science > Electrical and Computer Engineering
Item Type:Thesis (Masters)
Authors:Yasoubi, Monazzahalsadat
Institution:Concordia University
Degree Name:M.A. Sc.
Program:Electrical and Computer Engineering
Date:13 February 2020
Thesis Supervisor(s):Mohammad Reza, Soleymani
Keywords:LDPC code, DVBS2 standard, Hardware implementation, Vivado HLS.
ID Code:986490
Deposited By: Monazzahalsadat Yasoubi
Deposited On:26 Jun 2020 13:43
Last Modified:26 Jun 2020 13:43

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