On-Chip Inductance has become of significance in the design of high-speed interconnects. In this thesis, three techniques are applied to regenerate an RLC: interconnect in series, parallel and without regeneration. Simulations using a 0.25 om TSMC technology show that the parallel regeneration starts achieving a better speed than the non-regenerated line at wire lengths smaller than that achieved when the wire is serially regenerated. It also features 47% time delay saving and 96% Area-Delay product saving over the serial regeneration.  Repeaters are now widely used to enhance the performance of long On-Chip interconnects in CMOS VLSI. For RC-modeled interconnects, parallel repeaters have proved to be superior to serial ones. In this thesis, a Variable-Segment Regeneration Technique is introduced and compared with a Variable-Driver Parallel Technique, a recently proposed transparent repeater and with other three conventional techniques. HSpice Simulations using a 0.25 om TSMC technology show that both the variable-segment and variable-driver techniques feature 62% time delay saving and 354% Area-Delay product saving over the transparent repeater, and are superior to all conventional techniques. Moreover, our new variable-segment technique is characterized by a 116% Area-Delay product saving over the variable-driver technique. Thus, making it the most performant in the field of high-performance RLC interconnect regeneration. The simulation results and an analytical model of VSRT confirm the superiority of the parallel regeneration technique over the serial ones.