In this thesis, an accurate analytical model for DSM (Deep Sub-Micron) CMOS inverter short-circuit power estimation is presented. Compared with previous works, which always require extracted or fitting parameters, the proposed model depends only on the inverter dimension and SPICE parameters, which are usually provided with the given technology, resulting in the technology portability of this model. To achieve accurate modeling, the effect of the gate-to-drain coupling capacitance and some main DSM effects such as velocity saturation and mobility degradation are taken into account.  The accuracy and portability validations of the proposed model have been performed for UMC 1.2V 0.13om and TSMC 1.8V 0.18om CMOS technologies, and for a wide range of input transition times, output loading capacitances and aspect ratios. The results produced by the proposed model show good agreement with Spectre simulation using BSIM3v3.2 model in TSMC 1.8V 0.18om technologies, indicating its portability. Its accuracy is better than that of latest methods that require extraction. Based on a Maple implementation, the proposed model always offers much less average CPU time than Spectre simulator.