Computer networks are experiencing explosive growth which is reinforced by the recent
exhaustion of the global IPv4 addresses space in 2011 and the tenfold increase in users from 1999
to 2013. The advent of cloud, mobile and IoT is only going to accelerate this growth. This accedes
the need for flexible and scalable networks that process packets faster. Programmable packet
processing systems have emerged as a solution which aim to find balance between flexibility of
supporting different processing functions while maintaining a high processing capability.
Designing architectures that support such paradigms is fairly complicated as decisions need to be
made for evaluating trade-offs between flexibility and efficiency. Questions like what
programmatic interfaces, services, applications and protocols are required need to be answered
before synthesis of actual hardware. To evaluate such requirements modelling techniques are
required to evaluate architecture decisions accurately early enough in the design phase.
In this thesis, we propose a flexible system level modelling methodology for early
validation, design and analysis of packet processing applications for programmable forwarding
plane architectures. The hardware and software architecture is described in a high level language
which can be used to describe forwarding planes from many core network processors to
reconfigurable processing pipelines. Device architects can use this for design space exploration,
prototyping and validation; where application developers can start pre-silicon application design,
development and debugging to evaluate different hardware and software decisions in an industry
with ever shrinking market windows.