In at least a decade chip multiprocessors (CMP) have been dominating new commercial
releases due to computational advantages of parallel computing cores on a single chip. Network
on Chip (NoC) has emerged as an interconnection network of CMPs. But significant bandwidth
that is required for multicore chips is becoming a bottleneck in the traditional (electrical)
network on chip, due to delays caused by long wires in the electric NoC. Integration of photonic
links with traditional electronic interconnects proposes a promising solution for this challenge.
Since there are numerous design parameters for opto-electrical network architectures, an accurate
evaluation is needed to study the impact of each design parameter on network performance, and
to provide the most suitable network for a given set of applications, a power or a performance
goal. In this thesis, we present a prediction modeling technique for design space exploration of
an opto-electrical network on chip. Our proposed model accurately predicts delay (includes
network packet latency and network contention delay) and energy (includes static and dynamic
energy consumption) of the network. Specifically, this work addresses the fundamental challenge
of accurate estimation of desired metrics without having to incur high simulation cost of
numerous configurations of the optical network on chip architecture. We reduce the number of
required simulations by accurately selecting the parameters that have the most impact on the
network. Furthermore, we sparsely and randomly sample the designs build using these
parameters from an Optical Network on Chip (ONoC) design space, and simulate only the
sampled designs. We validate our model with three different applications executing on a large set
of network configurations in a large optical network on chip design space. We achieve average
error rates (root relative squared error) as low as 5.5% for the delay and 3.05% for the energy
consumption.