1. W. E. Vesely et al., "Fault tree handbook", 1981, [online] Available: https://www.nrc.gov/docs/ML1007/ML100780465.pdf. 2. H. Boudali, P. Crouzen, M. Stoelinga, "Dynamic fault tree analysis using input/output interactive Markov chains", Proc. IEEE/IFIP Int. Conf. Dependable Syst. Netw., pp. 708-717, Jun. 2007. 3. M. Walker et al., " Synthesis and analysis of temporal fault trees with PANDORA 1 : The time of Priority AND gates ", Nonlinear Anal. Hybrid Syst., vol. 2, pp. 368-382, Jun. 2008. 4. P. G. Wijayarathna, M. Maekawa, "Extending fault trees with an AND-THEN gate", Proc. Int. Symp. Softw. Rel. Eng., pp. 283-292, Oct. 2000. 5. M. Walker et al., "Compositional temporal fault tree analysis" in Computer Safety Reliability and Security, Berlin, Germany:Springer, pp. 106-119, 2007. 6. M. Walker et al., "A hierarchical method for the reduction of temporal expressions in pandora", Proc. 1st Workshop Dyn. Aspects Dependability Models Fault-Tolerant Syst., pp. 7-12, Apr. 2010. 7. E. Ruijters, M. Stoelinga, "Fault tree analysis: A survey of the state-of-the-art in modeling analysis and tools", Comput. Sci. Rev., vol. 15, pp. 29-62, Mar. 2015. 8. K. D. Rao, V. Gopika, V. V. S. Rao, H. S. Kushwaha, A. K. Verma, A. Srividya, "Dynamic fault tree analysis using monte carlo simulation in probabilistic safety assessment", Rel. Eng. Syst. Saf., vol. 94, no. 4, pp. 872-883, Apr. 2009. 9. J. Faulin et al., Simulation Methods for Releaty Availability Complex System, New York, NY, USA:Springer, 2010. 10. C. Dehnert et al., "A storm is coming: A modern probabilistic model checker", Proc. Int. Conf. Comput. Aided Verification, pp. 592-600, Sep. 2017. 11. F. Arnold et al., "Dftcalc: A tool for efficient fault tree analysis", Proc. Int. Conf. Comput. Saf. Rel. Secur., pp. 293-301, 2013. 12. M. Volk et al., Advancing dynamic fault tree analysis, 2016, [online] Available: https://arxiv.org/abs/1604.07474. 13. L. H. Mutuel, "Single event effects mitigation techniques report", 2016, [online] Available: https://www.faa.gov/aircraft/air_cert/design_approvals/air_software/media/TC-15-62.pdf. 14. S. Mukherjee, Archit. Design for Soft Errors, Burlington, MA, USA:Morgan Kaufmann, 2011. 15. C. Bottoni et al., "Heavy ions test result on a 65nm sparc-v8 radiation-hard microprocessor", Proc. IEEE Int. Rel. Phys. Symp., pp. 58-75, Aug. 2014. 16. K. J. Sullivan et al., "The galileo fault tree analysis tool", Proc. 29th Annu. Int. Symp. Fault-Tolerant Comput., pp. 232-235, Jun. 1999. 17. S. J. Schilling, Contribution to temporal fault tree analysis without modularization and transformation into the state space, 2015, [online] Available: https://arxiv.org/abs/1505.04511. 18. S. Kabir, M. Walker, Y. Papadopoulos, E. Rüde, P. Securius, "Fuzzy temporal fault tree analysis of dynamic systems", Int. J. Approx. Reasoning, vol. 77, pp. 20-37, Oct. 2016. 19. Z. Peng et al., "Risk assessment of railway transportation systems using timed fault trees", Qual. Rel. Eng. Int., vol. 32, no. 1, pp. 181-194, Feb. 2016. 20. A. David et al., "Uppaal SMC tutorial", Int. J. Softw. Tools Technol. Transf., vol. 17, no. 4, pp. 397-415, Aug. 2015. 21. E. Cheshmikhani, H. R. Zarandi, "Probabilistic analysis of dynamic and temporal fault trees using accurate stochastic logic gates", Microelectron. Rel., vol. 55, no. 11, pp. 2468-2480, Nov. 2015. 22. F. L. Kastensmidt et al., Fault-Tolerance Techniques for SRAM-Based FPGAs, New York, NY, USA:Springer, vol. 32, 2006. 23. P. Adell et al., "Analysis of single-event transients in analog circuits", IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2616-2623, Dec. 2000. 24. A. H. Johnston, G. M. Swift, T. F. Miyahira, L. D. Edmonds, "A model for single-event transients in comparators", IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2624-2633, Dec. 2000. 25. G. B. Hamad et al., "New insights into soft-faults induced cardiac pacemakers malfunctions analyzed at system-level via model checking", IEEE Access, vol. 6, pp. 62107-62119, 2018. 26. M. Kwiatkowska et al., "Performance analysis of probabilistic timed automata using digital clocks", Formal Methods Syst. Des., vol. 29, no. 1, pp. 33-78, Aug. 2006. 27. S. Friedenthal et al., A Practical Guide to SysML: System Modeing Language, Burlington, MA, USA:Morgan Kaufmann, 2014. 28. F. Mhenni et al., "Automatic fault tree generation from sysml system models", Proc. Int. Conf. Adv. Intell. Mechatron., pp. 715-720, 2014. 29. A. Wald, "Sequential tests of statistical hypotheses", Ann. Math. Statist., vol. 16, no. 2, pp. 117-186, 1945. 30. J. Bechta Dugan, S. J. Bavuso, M. A. Boyd, "Dynamic fault-tree models for fault-tolerant computer systems", IEEE Trans. Rel., vol. 41, no. 3, pp. 363-377, Sep. 1992. 31. F. Piedad, M. Hawkins, High Availability: Design Technical Processes, New York, NY, USA:Prentice Hall, 2001. 32. G. K. Palshikar, "Temporal fault trees", Inf. Softw. Technol., vol. 44, no. 3, pp. 137-150, 2002. 33. A. Rae et al., "A behaviour-based method for fault tree generation", Proc. Int. Syst. Saf. Conf. Syst. Saf. Soc., pp. 289-298, 2004. 34. The SPARC Architecture Manual: Version 8, Upper Saddle River, NJ, USA:Prentice-Hall, 1992. 35. M. Daněk et al., "The leon3 processor" in Exploring Fine-Grain Multi-Threading FPGAs, New York, NY, USA:Springer, pp. 9-14, 2013.