Among the various aspects of the UML, a state machine is part of the specification used to model the dynamic behavior of systems. In developing complex systems, state machines can be deployed to capture use cases and thus contribute towards requirements validation. During testing, a state machine can contribute towards requirements verification. In our proposal, we treat a state machine as a directed mathematical graph and transform it into a declarative model that is implemented as a database of clauses using Prolog. To tackle the complexity of composite states, we propose an algorithm for flattening the representation of a state machine. This model transformation occurs behind the scenes and provides the same semantic model at a lower level of abstraction. The initial and flattened declarative models provide the factbase on which we build a set of rules to study the behavior, the complexity and the structure of a state machine. 
Furthermore, we treat the machine’s flattened model as a platform over which we simulate the machine’s behavior given a scenario. We support the simulation process with a tool that we developed. The tool is implemented in Java using the Java Prolog Library (JPL) that provides an interface between the two technologies. Our simulator reads in a scenario and proceeds to generate the machine’s behavior including its state at discrete time steps as output. We demonstrate the process through a case study.