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Design and hardware implementation of a cooperative communication system


Design and hardware implementation of a cooperative communication system

Jia, Binbin (2007) Design and hardware implementation of a cooperative communication system. Masters thesis, Concordia University.

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Multiple Input, Multiple Output (MIMO) antenna systems have been widely studied. They play a key role in the next generation communication systems because of their capability to provide an extremely high capacity. However, the cost of using a large number of antennas should be considered when MIMO is put into practice. In order to reduce the cost of devices, there is another method called cooperative communication. In a cooperative communication system, each single antenna (node) shares its information with its nearby antennas (nodes), and then those antennas transmit together their data towards the destination, therefore, they generate a virtual MIMO system. In this thesis, we present a new framework, which is a combination of the detect-forward cooperative method, channel coding, and space time coding methods. We assume that the cooperative system includes an inter-user channel (between nodes) and an uplink channel (from the nodes to the destination) that are subject to independently distributed, slowly-varying and flat Rayleigh fading. Due to the fact that the inter-user channel is less noisy than the uplink channel, we apply the 16 QAM modulation in the inter-user channel in order to acquire higher data rate. In the uplink channel, one user and its collaborator send bits together to the destination. Therefore, Alamouti space time code can be used. To obtain a better performance and keep the same bandwidth, we utilize a Rate-compatible punctured convolutional code (RCPC). Simulation shows that improved performance can be achieved compared with that of a non-cooperative system. Based on this new system scheme, we implement the uplink receiver, which consists of a pair of parallel Square Root Raise Cosine (SRRC) filters, the Alamouti decoder, and the Viterbi decoder for decoding of the RCPC codes. In order to save the area, a parallel sequence of Alamouti decoder is controlled by the Moore state machine; a simplified method of the Branch Metric Unit (BMU) is introduced; the in-place scheduling is used in the Path Metric Unit (PMU). The design is modeled in Very high speed integrated circuit Hardware Description Language (VHDL) and synthesized on a single chip FPGA (Xilinx Virtex 2 Pro). According to the RTL level and the gate level simulation results, the receiver can work at a speed of 12 Mbps with Virtex 2 pro FPGA

Divisions:Concordia University > Gina Cody School of Engineering and Computer Science > Electrical and Computer Engineering
Item Type:Thesis (Masters)
Authors:Jia, Binbin
Pagination:xiii, 92 leaves : ill. ; 29 cm.
Institution:Concordia University
Degree Name:M.A. Sc.
Program:Electrical and Computer Engineering
Thesis Supervisor(s):Soleymani, M. Reza
Identification Number:LE 3 C66E44M 2007 J53
ID Code:975272
Deposited By: Concordia University Library
Deposited On:22 Jan 2013 16:05
Last Modified:13 Jul 2020 20:07
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