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Design and FPGA implementation of a SISO and a MIMO wireless system for software defined radio


Design and FPGA implementation of a SISO and a MIMO wireless system for software defined radio

Dong, Peng (2009) Design and FPGA implementation of a SISO and a MIMO wireless system for software defined radio. Masters thesis, Concordia University.

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MIMO (Multiple-input Multiple-output) technology combined with space time coding techniques provides significant increase in performance and capacity over an equivalent SISO (Single-input Single-output) system while maintaining the same bandwidth and transmission power. MIMO has emerged as the major breakthrough in recent communication technologies. To migrate from SISO to MIMO system, multiple RF (Radio Frequency) front ends and additional signal processing are required. Software defined radio (SDR) allows MIMO and other evolving techniques to be added to current systems through software update instead of hardware replacement. SDR provides a flexible and economic solution to the system upgrade and migration. In this thesis, an SDR based SISO system using QPSK modulation scheme is implemented on FPGA. The system produces signal with an intermediate frequency of 25 MHz and throughput of 12.5 Mbps. One carrier recovery and two symbol timing recovery algorithms (Gardner and Maximum Likelihood) are investigated and implemented. A 2x1 MIMO system using Alamouti scheme and CORDIC based carrier recovery is designed as well. The SDR based SISO system can be easily incorporated to the MIMO design. Throughout this thesis, detailed design information is presented along with both computer simulation results and real hardware performance. The comparisons of different algorithms and component structures are also provided. Based on these comparisons, the suitable algorithm or structure according to specific implementation considerations and system requirement can be selected. The design and implementation are processed based on a system-level design flow. System modeling and simulation are performed using Xilinx's System Generator for DSP and Simulink. After it is mapped to HDL (Hardware Description Language) netlist, the design is synthesized and implemented by Xilinx's ISE tool. The generated bit-stream is then downloaded to target FPGA to program the device. The hardware performance is measured by BER (Bit Error Rate) tester, oscilloscope and spectrum analyzer. This thesis is an initial project for future work of Wireless Design Laboratory at Concordia University. The system realized in this project can be viewed as a base of future MIMO implementation with different number of antennas and advanced signal processing techniques.

Divisions:Concordia University > Gina Cody School of Engineering and Computer Science > Electrical and Computer Engineering
Item Type:Thesis (Masters)
Authors:Dong, Peng
Pagination:xv, 104 leaves : ill. ; 29 cm.
Institution:Concordia University
Degree Name:M.A. Sc.
Program:Electrical and Computer Engineering
Thesis Supervisor(s):Shayan, Yousef R
Identification Number:LE 3 C66E44M 2009 D66
ID Code:976427
Deposited By: Concordia University Library
Deposited On:22 Jan 2013 16:25
Last Modified:13 Jul 2020 20:10
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