Nourivand, Afshin (2010) YieldAware Leakage Power Reduction of OnChip SRAMs. PhD thesis, Concordia University.

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Abstract
Leakage power dissipation of onchip static random access memories (SRAMs) constitutes a significant fraction of the total chip power consumption in stateoftheart microprocessors and systemonchips (SoCs). Scaling the supply voltage of SRAMs during idle periods is a simple yet effective technique to reduce their leakage power consumption. However, supply voltage scaling also results in the degradation of the cells’ robustness, and thus reduces their capability to retain data reliably. This is
particularly resulting in the failure of an increasing number of cells that are already weakened by excessive process parameters variations and/or manufacturing imperfections in nanometer technologies. Thus, with technology scaling, it is becoming increasingly challenging to maintain the yield while attempting to reduce the leakage
power of SRAMs. This research focuses on characterizing the yieldleakage tradeoffs and developing novel techniques for a yieldaware leakage power reduction of SRAMs.
We first demonstrate that new fault behaviors emerge with the introduction of a lowleakage standby mode to SRAMs. In particular, it is shown that there are some
types of defects in SRAM cells that start to cause failures only when the drowsy mode is activated. These defects are not sensitized in the active operating mode, and thus escape the traditional March tests. Fault models for these newly observed fault behaviors are developed and described in this thesis. Then, a new lowcomplexity test algorithm, called March RAD, is proposed that is capable of detecting all the drowsy faults as well as the simple traditional faults.
Extreme process parameters variations can also result in SRAM cells with very weak dataretention capability. The probability of such cells may be very rare in small memory arrays, however, in large arrays, their probability is magnified by the huge number of bitcells integrated on a single chip. Hence, it is critical also to account for such extremal events while attempting to scale the supply voltage of SRAMs. To estimate the statistics of such rare events within a reasonable computational time, we have employed concepts from extreme value theory (EVT). This has enabled us to accurately model the tail of the cell failure probability distribution versus the supply voltage. Analytical models are then developed to characterize the yieldleakage tradeoffs in large modern SRAMs. It is shown that even a moderate scaling of the supply voltage of large SRAMs can potentially result in significant yield losses, especially in processes with highly fluctuating parameters. Thus, we have investigated the application of faulttolerance techniques for a more efficient leakage reduction of SRAMs. These techniques allow for a more aggressive voltage scaling by providing tolerance to the failures that might occur during the sleep mode. The results show that in a 45nm technology, assuming 10% variation in transistors threshold voltage, repairing a 64KB memory using only 8 redundant rows or incorporating single error correcting codes (ECCs) allows for ~90% leakage reduction while incurring only ~1% yield loss. The combination of redundancy and ECC, however, allows to reach the practical limits of leakage reduction in the analyzed benchmark, i.e., ~95%.
Applying an identical standby voltage to all dies, regardless of their specific process parameters variations, can result in too many cell failures in some dies with heavily skewed process parameters, so that they may no longer be salvageable by the employed faulttolerance techniques. To compensate for the interdie variations, we
have proposed to tune the standby voltage of each individual die to its corresponding minimum level, after manufacturing. A test algorithm is presented that can be used to identify the minimum applicable standby voltage to each individual memory die. A possible implementation of the proposed tuning technique is also demonstrated. Simulation results in a 45nm predictive technology show that tuning standby voltage of SRAMs can enhance dataretention yield by an additional 10%−50%, depending on
the severity of the variations.
Divisions:  Concordia University > Faculty of Engineering and Computer Science > Electrical and Computer Engineering 

Item Type:  Thesis (PhD) 
Authors:  Nourivand, Afshin 
Institution:  Concordia University 
Degree Name:  Ph. D. 
Program:  Electrical and Computer Engineering 
Date:  October 2010 
Thesis Supervisor(s):  AlKhalili, Asim J. and Savaria, Yvon 
Keywords:  Static random access memories (SRAMs), dataretention failures (DRFs), minimum standby voltage, process variation, postsilicon tuning, yield enhancement, fault modeling, drowsy SRAM, lowpower design, open defects, weak cells, memory test, extreme failures, extreme value theory. 
ID Code:  7103 
Deposited By:  AFSHIN NOURIVAND 
Deposited On:  13 Jun 2011 13:49 
Last Modified:  13 Jun 2011 13:49 
References:  [1] J. Rabaey, Low Power Design Essentials. Springer, 2009.
[2] K. Zhang, Embedded Memories for NanoScale VLSIs. Springer, 2009. [3] A. Pavlov and M. Sachdev, CMOS SRAM Circuit Design and Parametric Test in NanoScaled Technologies. New York, USA: Springer, 2008. [4] S. Rusu, S. Tam, H. Muljono, J. Stinson, D. Ayers, J. Chang, R. Varada, M. Ratta, S. Kottapalli, and S. Vora, “A 45 nm 8core enterprise Xeon R processor,” SolidState Circuits, IEEE Journal of, vol. 45, no. 1, pp. 7 –14, jan. 2010. [5] International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 2009. [Online]. Available: http://www.itrs.net [6] R. Krishnarnurthy, A. Alvandpour, V. De, and S. Borkar, “Highperformance and lowpower challenges for sub70 nm microprocessor circuits,” in Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002, 2002, pp. 125 – 128. [7] C. Kenyon, A. Kornfeld, K. Kuhn, M. Liu, A. Maheshwari, W. Shih, S. Sivakumar, G. Taylor, P. VanDerVoorn, and K. Zawadzki, “Managing process variation in Intel’s 45nm CMOS technology,” Intel Technology Journal, vol. 12, no. 2, pp. 93–109, June 2008. [Online]. Available: http://www.intel.com/technology/itj/2008/v12i2/3managing/1abstract.htm [8] H. Yamauchi, “A discussion on SRAM circuit design trend in deeper nanometerscale technologies,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 18, no. 5, pp. 763 –774, may 2010. [9] Y. Ye, F. Liu, M. Chen, S. Nassif, and Y. Cao, “Statistical modeling and simulation of threshold variation under random dopant fluctuations and lineedge roughness,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. PP, no. 99, pp. 1 –10, 2010. [10] S. Nassif, “Modeling and analysis of manufacturing variations,” in Custom Integrated Circuits, 2001, IEEE Conference on., 2001, pp. 223 –228. 125 [11] R. Montanes, J. de Gyvez, and P. Volf, “Resistance characterization for weak open defects,” Design & Test of Computers, IEEE, vol. 19, no. 5, pp. 18–26, SepOct 2002. [12] J. M. Rabaey, A. Chandrakasan, , and B. Nikolic, Digital Integrated Circuits A Design Perspective, Second Edition. PrenticeHall, 2003. [13] L. Chang, R. Montoye, Y. Nakamura, K. Batson, R. Eickemeyer, R. Dennard, W. Haensch, and D. Jamsek, “An 8TSRAM for variability tolerance and lowvoltage operation in highperformance caches,” SolidState Circuits, IEEE Journal of, vol. 43, no. 4, pp. 956 –963, april 2008. [14] N. Verma and A. Chandrakasan, “A 65nm 8T subVt SRAM employing senseamplifier redundancy,” in SolidState Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, 1115 2007, pp. 328 –606. [15] I. J. Chang, J.J. Kim, S. Park, and K. Roy, “A 32 kb 10t subthreshold SRAM array with bitinterleaving and differential read scheme in 90 nm CMOS,” Solid State Circuits, IEEE Journal of, vol. 44, no. 2, pp. 650 –658, feb. 2009. [16] K. Roy, S. Mukhopadhyay, and H. MahmoodiMeimand, “Leakage current mechanisms and leakage reduction techniques in deepsubmicrometer CMOS circuits,” Proceedings of the IEEE, vol. 91, no. 2, pp. 305–327, Feb 2003. [17] Predictive Technology Model. [Online]. Available: http://ptm.asu.edu/ [18] F. Hamzaoglu, K. Zhang, Y. Wang, H. Ahn, U. Bhattacharya, Z. Chen, Y.G. Ng, A. Pavlov, K. Smits, and M. Bohr, “A 3.8 GHz 153 Mb SRAM design with dynamic stability enhancement and leakage reduction in 45 nm highk metal gate CMOS technology,” SolidState Circuits, IEEE Journal of, vol. 44, no. 1, pp. 148–154, Jan. 2009. [19] N. S. Kim, K. Flautner, D. Blaauw, and T. Mudge, “Circuit and microarchitectural techniques for reducing cache leakage power,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, no. 2, pp. 167–184, Feb. 2004. [20] H. Hanson, M. Hrishikesh, V. Agarwal, S. Keckler, and D. Burger, “Static energy reduction techniques for microprocessor caches,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, no. 3, pp. 303–313, June 2003. [21] A. Agarwal, H. Li, and K. Roy, “A singleVt lowleakage gatedground cache for deep submicron,” SolidState Circuits, IEEE Journal of, vol. 38, no. 2, pp. 319–328, Feb 2003. [22] J. Chang, M. Huang, J. Shoemaker, J. Benoit, S.L. Chen, W. Chen, S. Chiu, R. Ganesan, G. Leong, V. Lukka, S. Rusu, and D. Srivastava, “The 65nm 16 MB shared ondie L3 cache for the dualcore Intel Xeon processor 7100 series,” SolidState Circuits, IEEE Journal of, vol. 42, no. 4, pp. 846–852, April 2007. 126 [23] H. Mizuno and T. Nagano, “Driving sourceline cell architecture for sub1V highspeed lowpower applications,” SolidState Circuits, IEEE Journal of, vol. 31, no. 4, pp. 552 –557, apr 1996. [24] C. Kim and K. Roy, “Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors,” in Low Power Electronics and Design, 2002. ISLPED ’02. Proceedings of the 2002 International Symposium on, 2002, pp. 251 – 254. [25] Y. Wang, H. J. Ahn, U. Bhattacharya, Z. Chen, T. Coan, F. Hamzaoglu, W. Hafez, C.H. Jan, P. Kolar, S. Kulkarni, J.F. Lin, Y.G. Ng, I. Post, L. Wei, Y. Zhang, K. Zhang, and M. Bohr, “A 1.1 Ghz 12 μ A/Mbleakage SRAM design in 65 nm ultralowpower CMOS technology with integrated leakage reduction for mobile applications,” SolidState Circuits, IEEE Journal of, vol. 43, no. 1, pp. 172–179, Jan. 2008. [26] T.H. Kim, J. Liu, and C. Kim, “A voltage scalable 0.26 V, 64 kb 8T SRAM with Vmin lowering techniques and deep sleep mode,” SolidState Circuits, IEEE Journal of, vol. 44, no. 6, pp. 1785–1795, June 2009. [27] J. Tschanz, S. Narendra, Y. Ye, B. Bloechel, S. Borkar, and V. De, “Dynamic sleep transistor and body bias for active leakage power control of microprocessors,” SolidState Circuits, IEEE Journal of, vol. 38, no. 11, pp. 1838 – 1845, nov. 2003. [28] A. Nourivand, C. Wang, and M. Omair Ahmad, “An adaptive sleep transistor biasing scheme for low leakage SRAM,” in Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, 2730 2007, pp. 2790 –2793. [29] Y. Meng, T. Sherwood, and R. Kastner, “Exploring the limits of leakage power reduction in caches,” ACM Trans. Archit. Code Optim., vol. 2, no. 3, pp. 221– 246, 2005. [30] M. Sharifkhani and M. Sachdev, “Segmented virtual ground architecture for lowpower embedded SRAM,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 15, no. 2, pp. 196 –205, feb. 2007. [31] K.S. Min, K. Kanda, and T. Sakurai, “Rowbyrow dynamic sourceline voltage control (RRDSV) scheme for two orders of magnitude leakage current reduction of sub1VVDD SRAM’s,” in Low Power Electronics and Design, 2003. ISLPED ’03. Proceedings of the 2003 International Symposium on, Aug. 2003, pp. 66–71. [32] E. Seevinck, F. List, and J. Lohstroh, “Staticnoise margin analysis of MOS SRAM cells,” SolidState Circuits, IEEE Journal of, vol. 22, no. 5, pp. 748–754, Oct 1987. [33] M. Powell, S.H. Yang, B. Falsafi, K. Roy, and T. Vijaykumar, “GatedVdd: a circuit technique to reduce leakage in deepsubmicron cache memories,” Low 127 Power Electronics and Design, 2000. ISLPED ’00. Proceedings of the 2000 International Symposium on, pp. 90–95, 2000. [34] S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS,” ComputerAided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, no. 12, pp. 1859–1880, Dec. 2005. [35] A. Pavlov, M. Sachdev, and J. De Gyvez, “Weak cell detection in deepsubmicron SRAMs: A programmable detection technique,” SolidState Circuits, IEEE Journal of, vol. 41, no. 10, pp. 2334–2343, Oct. 2006. [36] J. Segura, A. Keshavarzi, J. Soden, and C. Hawkins, “Parametric failures in CMOS ICs  a defectbased analysis,” in Test Conference, 2002. Proceedings. International, 2002, pp. 90–99. [37] K. Agarwal and S. Nassif, “Characterizing process variation in nanometer CMOS,” in DAC ’07: Proceedings of the 44th annual Design Automation Conference. New York, NY, USA: ACM, 2007, pp. 396–399. [38] K. Bowman, S. Duvall, and J. Meindl, “Impact of dietodie and withindie parameter fluctuations on the maximum clock frequency distribution for gigascale integration,” SolidState Circuits, IEEE Journal of, vol. 37, no. 2, pp. 183 –190, feb 2002. [39] P. Stolk, F. Widdershoven, and D. Klaassen, “Modeling statistical dopant fluctuations in MOS transistors,” Electron Devices, IEEE Transactions on, vol. 45, no. 9, pp. 1960 –1971, sep. 1998. [40] A. Bhavnagarwala, X. Tang, and J. Meindl, “The impact of intrinsic device fluctuations on CMOS SRAM cell stability,” SolidState Circuits, IEEE Journal of, vol. 36, no. 4, pp. 658–665, Apr 2001. [41] H. Qin, Y. Cao, D. Markovic, A. Vladimirescu, and J. Rabaey, “SRAM leakage suppression by minimizing standby supply voltage,” Quality Electronic Design, 2004. Proceedings. 5th International Symposium on, pp. 55–60, 2004. [42] J. Wang, A. Singhee, R. Rutenbar, and B. Calhoun, “Statistical modeling for the minimum standby supply voltage of a full SRAM array,” in Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European, Sept. 2007, pp. 400–403. [43] A. Kumar, H. Qin, P. Ishwar, J. Rabaey, and K. Ramchandran, “Fundamental data retention limits in SRAM standby  experimental results,” in Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on, March 2008, pp. 92–97. [44] ——, “Fundamental bounds on power reduction during dataretention in standby SRAM,” in Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, May 2007, pp. 1867–1870. 128 [45] H. Qin, A. Kumar, K. Ramchandran, J. Rabaey, and P. Ishwar, “Errortolerant SRAM design for ultralow power standby operation,” in ISQED ’08: Proceedings of the 9th international symposium on Quality Electronic Design. Washington, DC, USA: IEEE Computer Society, 2008, pp. 30–34. [46] S. Hamdioui and A. Van De Goor, “An experimental analysis of spot defects in SRAMs: realistic fault models and tests,” Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian, pp. 131–138, 2000. [47] A. Singhee and R. Rutenbar, “Statistical blockade: Very fast statistical simulation and modeling of rare circuit events and its application to memory design,” ComputerAided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, no. 8, pp. 1176–1189, Aug. 2009. [48] R. Kanj, R. Joshi, and S. Nassif, “Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events,” in Design Automation Conference, 2006 43rd ACM/IEEE, 00 2006, pp. 69–72. [49] L. Ding and P. Mazumder, “The impact of bitline coupling and ground bounce on cmos sram performance,” in VLSI Design, 2003. Proceedings. 16th International Conference on, jan. 2003, pp. 234 – 239. [50] J. Yang, B. Wang, Y. Wu, and A. Ivanov, “Fast detection of data retention faults and other SRAM cell open defects,” ComputerAided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, no. 1, pp. 167–180, Jan. 2006. [51] L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, S. Borri, and M. Hage Hassan, “Resistiveopen defects in embeddedSRAM core cells: analysis and march test solution,” Test Symposium, 2004. 13th Asian, pp. 266–271, Nov. 2004. [52] T. Mak, D. Bhattacharya, C. Prunty, B. Roeder, N. Ramadan, J. Ferguson, and J. Yu, “Cache RAM inductive fault analysis with fab defect modeling,” Test Conference, 1998. Proceedings., International, pp. 862–871, Oct 1998. [53] A. van de Goor and Z. AlArs, “Functional memory faults: a formal notation and a taxonomy,” VLSI Test Symposium, 2000. Proceedings. 18th IEEE, pp. 281–289, 2000. [54] W. Pei, W.B. Jone, and Y. Hu, “Fault modeling and detection for drowsy SRAM caches,” ComputerAided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 26, no. 6, pp. 1084–1100, June 2007. [55] P. Embrechts, T. Mikosch, and C. Kl¨uppelberg, Modelling Extremal Events: For Insurance and Finance. London, UK: SpringerVerlag, 1997. 129 [56] H. Qin, Y. Cao, D. Markovic, A. Vladimirescu, and J. Rabaey, “SRAM leakage suppression by minimizing standby supply voltage,” in ISQED ’04: Proceedings of the 5th International Symposium on Quality Electronic Design. Washington, DC, USA: IEEE Computer Society, 2004, pp. 55–60. [57] S. Ghosh, S. Mukhopadhyay, K. Kim, and K. Roy, “Selfcalibration technique for reduction of hold failures in lowpower nanoscaled SRAM,” in DAC ’06: Proceedings of the 43rd annual Design Automation Conference. New York, NY, USA: ACM, 2006, pp. 971–976. [58] A. Nourivand, A. AlKhalili, and Y. Savaria, “Aggressive leakage reduction of SRAMs using error checking and correcting (ECC) techniques,” in Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on, 1013 2008, pp. 426 –429. [59] A. Singhee, J. Wang, B. Calhoun, and R. Rutenbar, “Recursive statistical blockade: An enhanced technique for rare event simulation with application to SRAM circuit design,” in VLSI Design, 2008. VLSID 2008. 21st International Conference on, jan. 2008, pp. 131 –136. [60] A. Agarwal, D. Blaauw, and V. Zolotov, “Statistical timing analysis for intradie process variations with spatial correlations,” in Computer Aided Design, 2003. ICCAD2003. International Conference on, Nov. 2003, pp. 900–907. [61] A. Agarwal, B. Paul, S. Mukhopadhyay, and K. Roy, “Process variation in embedded memories: failure analysis and variation aware architecture,” SolidState Circuits, IEEE Journal of, vol. 40, no. 9, pp. 1804 – 1814, sept. 2005. [62] J. Hennessy and D. Patterson, Computer Architecture  A Quantitative Approach, 3rd Edition. San Mateo, CA: Morgan Kaufmann, 2003. [63] C. Stapper and H.S. Lee, “Synergistic faulttolerance for memory chips,” Computers, IEEE Transactions on, vol. 41, no. 9, pp. 1078–1087, Sep 1992. [64] C. L. Chen and M. Y. Hsiao, “Errorcorrecting codes for semiconductor memory applications: a stateoftheart review,” IBM J. Res. Dev., vol. 28, no. 2, pp. 124–134, 1984. [65] R. A. Fisher and L. H. C. Tippett, “Limiting forms of the frequency distribution of the largest or smallest member of a sample,” Proceedings of the Cambridge Philosophical Society, vol. 44, no. 1, pp. 180–190, Apr. 1928. [66] J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, and V. De, “Adaptive body bias for reducing impacts of dietodie and withindie parameter variations on microprocessor frequency and leakage,” SolidState Circuits, IEEE Journal of, vol. 37, no. 11, pp. 1396–1402, Nov 2002. 130 [67] J. Tschanz, S. Narendra, R. Nair, and V. De, “Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors,” SolidState Circuits, IEEE Journal of, vol. 38, no. 5, pp. 826–829, May 2003. [68] S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Reduction of parametric failures in sub100nm SRAM array using body bias,” ComputerAided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 27, no. 1, pp. 174–183, Jan. 2008. [69] M. Khellah, D. Somasekhar, Y. Ye, N. S. Kim, J. Howard, G. Ruhl, M. Sunna, J. Tschanz, N. Borkar, F. Hamzaoglu, G. Pandya, A. Farhang, K. Zhang, and V. De, “A 256Kb dualVCC SRAM building block in 65nm CMOS process with actively clamped sleep transistor,” SolidState Circuits, IEEE Journal of, vol. 42, no. 1, pp. 233 –242, jan. 2007. [70] Y.Wang, U. Bhattacharya, F. Hamzaoglu, P. Kolar, Y.G. Ng, L.Wei, Y. Zhang, K. Zhang, and M. Bohr, “A 4.0 GHz 291 Mb voltagescalable SRAM design in a 32 nm highk + metalgate CMOS technology with integrated power management,” SolidState Circuits, IEEE Journal of, vol. 45, no. 1, pp. 103 –110, jan. 2010. [71] S. Ghosh, S. Mukhopadhyay, K. Kim, and K. Roy, “Selfcalibration technique for reduction of hold failures in lowpower nanoscaled sram,” in Design Automation Conference, 2006 43rd ACM/IEEE, 00 2006, pp. 971–976. [72] N. Mojumder, S. Mukhopadhyay, J.J. Kim, C.T. Chuang, and K. Roy, “Selfrepairing SRAM using onchip detection and compensation,” Very Large Scale Integration (VLSI) Sy 
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