Lammoshi, Tawfeeq (2003) Modeling and design of parallel regeneration techniques for high-speed SOC RLC interconnects. Masters thesis, Concordia University.
On-Chip inductance has become of significance in the design of high-speed interconnects. Repeaters are now widely used to enhance the performance of long On-Chip interconnects in CMOS SOC/VLSI. These repeaters are inserted in the interconnect according to a criterion. One example of criterion is to insert the repeaters so as to keep the signal driving capability uniform along the interconnect. While the size of the repeaters is kept constant, the length of the interconnect segments is increased when we move towards the interconnect end. This technique is called VSRT (Variable-Segment Regeneration Technique). Moreover, in order to calculate optimal design parameters, while saving a large numbers of electrical simulations, two models of the repeater are compared in this thesis: a transistor-based model and, a parallel-resistance RC-based model for which an analytical model was developed. The technology used in our experimentation is a 0.5 om (Taiwan Semiconductor Manufacturing Company) TSMC technology, and the simulation was performed using HSPICE. The simulation results showed that our parallel-resistance RC-based VSRT gives accurate results. A software package was extracted from the analytical model to advice the designer on how to optimally set design parameters.
|Divisions:||Concordia University > Faculty of Engineering and Computer Science > Electrical and Computer Engineering|
|Item Type:||Thesis (Masters)|
|Pagination:||ix, 73 leaves : ill. ; 29 cm.|
|Degree Name:||Theses (M.A.Sc.)|
|Program:||Electrical and Computer Engineering|
|Thesis Supervisor(s):||Nekili, Mohamed|
|Deposited By:||Concordia University Libraries|
|Deposited On:||27 Aug 2009 17:25|
|Last Modified:||08 Dec 2010 15:24|
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