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A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform

Title:

A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform

Zhang, Chengjun, Wang, Chunyan and Ahmad, M. Omair (2012) A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform. IEEE Transactions on Circuits and Systems I: Regular Papers, 59 (8). pp. 1775-1785. ISSN 1549-8328

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Official URL: http://dx.doi.org/10.1109/TCSI.2011.2180432

Abstract

In this paper, a scheme for the design of a high-speed pipeline VLSI architecture for the computation of the 2-D discrete wavelet transform (DWT) is proposed. The main focus in the development of the architecture is on providing a high operating frequency and a small number of clock cycles along with an efficient hardware utilization by maximizing the inter-stage and intra-stage computational parallelism for the pipeline. The inter-stage parallelism is enhanced by optimally mapping the computational task of multi decomposition levels to the stages of the pipeline and synchronizing their operations. The intra-stage parallelism is enhanced by dividing the 2-D filtering operation into four subtasks that can be performed independently in parallel and minimizing the delay of the critical path of bit-wise adder networks for performing the filtering operation. To validate the proposed scheme, a circuit is designed, simulated, and implemented in FPGA for the 2-D DWT computation. The results of the implementation show that the circuit is capable of operating with a maximum clock frequency of 134 MHz and processing 1022 frames of size 512 × 512 per second with this operating frequency. It is shown that the performance in terms of the processing speed of the architecture designed based on the proposed scheme is superior to those of the architectures designed using other existing schemes, and it has similar or lower hardware consumption.

Divisions:Concordia University > Gina Cody School of Engineering and Computer Science > Electrical and Computer Engineering
Item Type:Article
Refereed:Yes
Authors:Zhang, Chengjun and Wang, Chunyan and Ahmad, M. Omair
Journal or Publication:IEEE Transactions on Circuits and Systems I: Regular Papers
Date:2012
Digital Object Identifier (DOI):10.1109/TCSI.2011.2180432
ID Code:981317
Deposited By: CHUNYAN WANG
Deposited On:08 Jun 2016 19:47
Last Modified:18 Jan 2018 17:52
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