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A High-speed and Low Power Electrical Link Transceiver

Title:

A High-speed and Low Power Electrical Link Transceiver

Jia, Xiangdong (2017) A High-speed and Low Power Electrical Link Transceiver. Masters thesis, Concordia University.

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Abstract

On-chip wires will present increasing latency and energy problems as VLSI technologies continue to scale. Interconnects have an RC-limited bandwidth approximately proportional to the area of the metal cross section and inversely proportional to the squared length. To overcome RC-limited channels, an energy-efficient on-chip transceiver is presented that contains a hybrid transmitter, a current-sense receiver, and self-testing blocks. The main goal of this research is having a relatively low-power transceiver, which can be used as an on-chip communication system.
By adding a pre-emphasis circuit in the transmitter, pre-cursor inter-symbol interference can be canceled. A hybrid transmitter which combines voltage-mode pre-emphasis with a current-mode main driver is used. This structure can save pre-emphasis current, and leads to reduced power dissipation especially in the static situation. A current-sense amplifier is implemented with a cross-coupled stage and an active inductor equalizer at the receiver, in order to boost the data rate while maintaining good energy efficiency. An offset cancelation circuit is incorporated to make a robust comparator for the receiver. According to simulation results, the transceiver has low power consumption with 1.2 V, 130 nm CMOS technology. The performance shows that it operates at 8 Gb/s over a 5 mm and 19 dB loss differential channel. The overall dynamic power consumption is 2.05 mW, without the PRBS generator/checker. Therefore, this transceiver has high data rate and low power consumption.

Divisions:Concordia University > Gina Cody School of Engineering and Computer Science > Electrical and Computer Engineering
Item Type:Thesis (Masters)
Authors:Jia, Xiangdong
Institution:Concordia University
Degree Name:M.A. Sc.
Program:Electrical and Computer Engineering
Date:March 2017
Thesis Supervisor(s):Cowan, Glenn
ID Code:982490
Deposited By: XIANGDONG JIA
Deposited On:09 Jun 2017 14:08
Last Modified:18 Jan 2018 17:55
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