Abstract

Symbol timing recovery (STR) is required in every digital synchronous communications receiver, since the output of the demodulator must be sampled periodically at symbol rate, at the precise sampling time instants in order to correctly recover the transmitted data. The major objective of this thesis is to present, analyze and prove feasibility of the new, low complexity, digital implementation structures for STR. The first presented digital structure is a feedback (FB) symbol timing recovery technique, which is based on the Costas loop principle. This technique requires only 5 constant multipliers and 7 adders, and has very low jitter feature, which is very desirable for high level modulation techniques. The structure, with its error tracking capabilities, is perfectly applicable for continuous mode communication systems, however, the required long acquisition time, makes this feedback STR not suitable for short burst mode communication systems. The feedforward (FF) STR techniques, have very short acquisition time, thus they are the perfect candidates for the short burst mode communication systems, and two such FF techniques are presented in this thesis as well. The first presented FF technique uses relatively high symbol over-sampling (16 samples per symbol) to achieve low implementation complexity (2 unsigned adders, 1 RAM block, and 1 serial magnitude comparator), and acceptable jitter, with the help of only 4 symbols long training preamble. Due to high over-sampling rate, the technique is only applicable to communication systems with relatively low bit rate. In order to expand the applicability of this new over-sampling, technique to higher bit rate systems, an optional "add-on" interpolation technique is presented, which can effectively reduce the over-sampling rate to a minimum of 3 samples per symbol. The cost for the improved performance is in the increased implementation complexity (additional 3 summers and 1 divider)