Abstract

Delay-insensitive (DI) circuits are asynchronous circuits whose functional correctness is independent of the delays in their components and the interconnecting wires. The environment and circuit module follows a specified usage protocol, sometimes called handshake signals. It has been believed that purely DI circuits are easy to test because any fault will prevent the generation of an acknowledge signal. We show that this is not always true under a general set of components. A Petri net fault model is used to reveal the possibility of critical races/hazards during test. A design for test method using observation points is shown which guarantees 100% fault coverage, and structural theorems are proved which can reduce/eliminate these observation points. No automated techniques exist so far for reducing the test length of these circuits, in particular, two-phase transition signaling circuits which contain implicit state encoding. Since there can be very few combinational components, classic scan design would not apply. A theory for control point insertion is presented for test length reduction. The major difficulty is in deriving a safe hazard-free test; the specified usage protocol does not directly apply because of the alterations made. Algorithms based on partial order protocol extraction and partial states are presented which produce provably correct test behaviors. Finally, an impossibility result is proved for fault tolerance in the most common class of DI circuit.