Abstract

In order to meet the incessantly growing demand of performance, the amount of embedded or on-chip memory in microprocessors and systems-on-chip (SOC) is increasing. As much as 70% of the chip area is now dedicated to the embedded memory, which is primarily realized by the static random access memory (SRAM). Because of the large size of the SRAM, its yield and leakage power consumption dominate the overall yield and leakage power consumption of the chip. However, as the CMOS technology continues to scale in the sub-65 nanometer regime to reduce the transistor cost and the dynamic power, it poses a number of challenges on the SRAM design. In this thesis, we address these challenges and propose cell-level and architecture level solutions to increase the yield and reduce the leakage power consumption of the SRAM in nanoscale CMOS technologies.
The conventional six transistor (6T) SRAM cell inherently suffers from a trade-off between the read stability and write-ability because of using the same bit line pair for both the read and write operations. An optimum design at a given process and voltage condition is a key to ensuring the yield and reliability of the SRAM. However, with technology scaling, process-induced variations in the transistor dimensions and electrical parameters coupled with variation in the operating conditions make it difficult to achieve a reasonably high yield. In this work, a gated SRAM architecture based on a seven transistor (7T) SRAM bit-cell is proposed to address these concerns. The proposed cell decouples the read bit line from the write bit lines. As a result, the storage node is not affected by any read induced noise during the read operation. Consequently, the proposed cell shows higher data stability and yield under varying process, voltage, and temperature (PVT) conditions. A single-ended sense amplifier is also presented to read from the proposed 7T cell while a unique write mechanism is used to reduce the write power to less than half of the write power of the conventional 6T cell. The proposed cell consumes similar silicon area and leakage power as the 6T cell when laid out and simulated using a commercial 65-nm CMOS technology. However, as much as 77% reduction in leakage power can be achieved by coupling the 7T cell with the column virtual grounding (CVG) technique, where a non-zero voltage is applied to the source terminals of driver NMOS transistors in the cell. The CVG technique also enables implementing multiple words per row, which is a key requirement for memories to avoid multiple-bit data upset in the event of radiation induced single event upset or soft error. In addition, the proposed cell inherently has a 30% larger soft error critical charge, making its soft error rate (SER) less than the half of that of the 6T cell.