Abstract

Abstract
A Dynamic Back End of the Line Customization Technique for
Yield Improvement
Ardavan Aryanpour, M. Sc
July 2010
As CMOS technology evolves and transistors get smaller, although chip
manufacturers benefit significantly from being able to fit more transistors in a
smaller area and also producing chips with lower power dissipation, they have
to confront newer problems that are directly related to the size of transistors
and the thickness of the deposited layers on a wafer.
Smaller transistors are faster and dissipate less power, but the smaller the
technology becomes, the harder the fabrication process is to control. Thin
silicon, metal and oxide layers must be accurately deposited because any
variation in the thickness will cause unexpected behavior in the device.
These variations affect many parameters in CMOS. Any slight change in
temperature, doping density, deposition timing, etc., can cause a significant
change of characteristics of a CMOS device and the variation caused by these
changes is called Process Variation (PV).
In this thesis, two circuits are taken into study in order to understand how
process variation impacts the electrical specifications of a circuit example.
The first example is a tapered buffer chain and the second example is a senseamplifier
flip flop. The idea is to propose a technique to decrease the loss
percentage (Increase the yield). Basically for one specific design a few variant
circuit layouts with different power-speed specifications are implemented and
based on the results of the mid fabrication measurements on the test circuits
that are deposited throughout the wafer, one of them is chosen with the means
of choosing a proper masking sequence. The electrical characteristics of the
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