Abstract

In this thesis, a prototype design for the Physical Layer of IEEE 802.11a standard, which is based on Orthogonal Frequency Division Multiplexing (OFDM) technique, is presented. Implementation aspects of an OFDM modem on Xilinx Virtex II field programmable gate array (FPGA) are addressed. The system includes a synchronization circuitry used for packet detection and time synchronization. The design flow starts with floating-point modeling with parameters specified by IEEE 802.11a for the physical layer of indoor Wireless Local Area Network (WLAN) modems. After algorithmic exploration and performance simulations, the fixed-point refinement is verified to compromise between sufficient arithmetic precision and high-speed hardware necessary for real-time communication systems. At this step of design, different synchronization schemes are examined and as the result of comparison; a modified algorithm based on the delayed correlation of received preamble symbols is selected for hardware implementation. Finally, the architecture with lowest power consumption and required speed specified by the standard is achieved. This design is efficiently synthesized on 0.15om/0.12om CMOS 8-layer metal process Virtex II FPGA. The resulting hardware implementation is simulated at the system clock speed of 72MHz and analyzed from timing point of view to verify adequate performance.