Abstract

Digital video processing algorithms are computationally intensive and their performance worsens dramatically as image resolution and pixel data size grow larger. Effective techniques are required to contend with this shortcoming in performance. One solution is to make use of a fast-prototyping, flexible and reprogrammable Field Programmable Gate Array (FPGA) technology. This thesis proposes an FPGA implementation of a video noise estimation algorithm capable of real-time processing. The objectives of this thesis consist of adapting a computationally demanding noise estimation algorithm to a synthesizable VHDL design and achieving real-time processing performance. Hardware feasibility is determined through a study of the mathematical operations used in the estimation process. The proposed architecture provides a satisfactory compromise between area and processing speed. Furthermore, parameterization of the architecture allows additional flexibility with the scaling of features, such as filter size, to operate on 3 x 3 or 5 x 5 blocks of pixels