Abstract

Today leading VLSI experts predict a hard wall for CMOS and other conventional fabrication technology due to fundamental physical limits (ultra-thin gate oxide, short channel effects, doping fluctuations, etc.), and increasingly difficult and expensive lithography in nanoscale. Extensive research conducted in recent years at nanoscale aiming to surpass CMOS has proposed Quantum Dot Cellular Automata as a viable alternative for nanoscale computing. Quantum Dot Cellular Automata (QCA) paradigm is an innovatory approach to computing, which encodes binary information by means of charge configuration of nanostructures instead of current switching devices. The fundamental building block of QCA devices is the QCA cell, and electrostatic interaction between neighboring cells governs the design of all QCA wires and logic gates. The two primary logic elements in QCA technology are: majority voter and inverter. Binary wires and inverter chains are used for interconnection purposes. Logic operation AND, and OR can be achieved by maneuvering inputs to the majority voter. Clocking enables precise control over timing and data flow direction, as well as power gain in QCA circuits. Also proper clocking can achieve computational pipelining and can drastically reduce circuit power dissipation. Manufacturing of a QCA cell is expected to result in defects like cell displacement, misalignment, and absence of cell or additional cell in circuitry, causing the circuit to exhibit faulty behavior. So a well-defined testing scheme becomes necessary for this technology. Though the technology is different from conventional CMOS design, it is shown to be effective and realistic to use existing testing schemes at this stage. Stuck-at (s-a-v) fault model is quite acceptable in this regard in spite of the fact, that this model does not incorporate all the defective behaviors occurring in the fabrication process. With this in view, single stuck-at value faults have been considered for testing QCA circuits. In this thesis a new strategy for designing QCA logic, exhaustively testable for single s-a-v faults, is presented. In particular, the method facilitates QCA functionality testing. Any combinational logic can be implemented using only AND-OR gates (with negated signals available), and in QCA this generally results in reduced test set for exhaustive fault detection within the data path. Previously this strategy was used for QCA logic testing considering only primary inputs (either true or complemented, but not both) feeding different majority voters, which fails for general circuits where fanouts are allowed for primary inputs and their complement. Here, a design scheme has been proposed which makes testing possible for any combinational QCA circuit. The extension to modular design testing is also presented. Two design approaches are proposed for testing modular and non-modular logic. The first design uses 2 n ( n = primary inputs) ' Test Enable ' majority voters, and is tested with two 4-bit vectors regardless of complexity of design and the input size. Second design employs n majority voters for the same purpose, thus requiring lesser number of majority voters, but at the price of increased vector length. Application specific conditions would decide which design becomes optimal. Without going into the features of a particular QCA fabrication, errors on logic level is addressed, such that the approach achieves generality, and could be applied to any particular implementation of QCA. Also to overcome the fault masking in modular circuit design, a solution has been presented. To verify the scheme, a simulation and layout tool, QCADesigner version 2.0.3 was used. First the fault free circuit was designed and simulated. Then random s-a-v faults were injected in different locations of data path. In all cases, 100% fault coverage was achieved confirming the validity of proposed approach