Abstract

With deeper and faster VLSI technologies, on-chip inductance has gained significance in the design of high-speed interconnects. This work reviews the importance of on-chip inductance, its useful effects and the associated negative drawbacks. It also gives an overview of the existing RC/RLC interconnect delay models and repeater insertion methodologies. The rapid growth in the VLSI technology has led to continuos reduction in the feature size of the VLSI devices and thus to higher levels of integration. The increased speed of on-chip circuitry has caused the time required for a signal to travel through the long onchip interconnects to become a significant portion of the total delay in a processing unit. Repeaters are now widely used to enhance the performance of these interconnects in CMOS SoC. For RC-modeled interconnects, parallel repeaters have proved to be superior to their serial counterparts. In this thesis, a Variable-Repeater Regeneration Technique (VRRT) and the associated mathematical models for the delays are presented. These models are used to confirm the speed optimality of the interconnects resulting from VRRT. The mathematical formulation is based on modeling the repeater resistance in series with the interconnect and also based on the first and second moment analysis, which takes into account the inductive effects of the interconnects. The main focus of this dissertation is to present a theory in parallel repeater modeling for repeater-insertion regeneration strategies. Hence, in order to avoid the fundamental weaknesses associated with the serial modeling of a parallel repeater, we carry out a new mathematical modeling for parallel repeater-insertion methodologies in SoC Interconnects. The proposed methodology is based on modeling the repeater pull-down resistance in parallel with the interconnect. Also, to account for the effect of interconnect inductance, two moments are used in the transfer function, as opposed to the previously reported Elmore delay models, which consider only one moment for the RC interconnects. The new parallel modeling technique is applied to both the Variable-Segment Regeneration Technique (VSRT) and Variable-Repeater Regeneration Technique. A direct consequence of this new type of modeling is an increased challenge in the mathematical modeling of the interconnects. HSpice electrical and C++/MATLAB simulations are conducted to assess the performance of the proposed optimization methodology using 0.25-micron CMOS technology. Simulation results show that the proposed repeater-insertion methodology can be used to optimize SoC interconnects in terms of propagation delay, and provide the VLSI/SoC designers with optimal design parameters, such as type, position and size of the repeaters, to be used for the interconnect regeneration, faster than by using the conventional HSpice simulations. Also in this dissertation, a new technique of regeneration, the Hybrid Regeneration Technique (HRT), is introduced. This technique is expected to perform better than the VSRT and VRRT, since it combines the advantages of the latter two techniques. Both the serial and parallel repeater modeling techniques are applied to HRT. Finally, a framework for a CAD tool based on the serial and parallel modeling of repeaters is presented