Abstract

The use of multiple antennas at the transmitter and the receiver can significantly increase the data rate and reliability of communications over wireless channels. With constraints in practical implementations, transmission techniques are designed to achieve a certain trade-off between transmission rates and implementation complexity. Layered space time (LST) architecture achieves high data transmission rates in multiple-input multiple-output (MIMO) systems with reasonable complexity through separate multi-user detection and decoding. However, LST architecture is suboptimal since the redundancy in error correcting codes is not fully exploited in detection. This suggests improvements to the existing LST design are possible. Multi-level coding (MLC), which achieves the channel capacity based on the information chain rule, has been applied in MIMO communications for improved performance. In practice, however, rate optimization is difficult to implement. In this thesis, we consider improved LST architecture that provides better performance without increasing the implementation complexity. For improved performance, we propose the use of multi-stage decoding (MSD) in the LST receiver. The use of MSD exploits the inherent redundancy in error correcting codes in data detection and effectively applies the idea of multi-level coding (MLC). In addition, we propose unequal transmit power allocation to achieve equal capacities among layers. The introduction of transmit power as an additional dimension in design adds more flexibility to the design process and improves performance without increasing implementation complexity. Based on the notion of unequal power allocation, an improved LST architecture is proposed. The power allocation required to achieve equal capacities among layers in LST architecture is derived. The theoretical analysis of the proposed unequal power allocation is carried out for both fast and quasi-static fading channels based on different criteria. Performance analysis of the proposed approach is conducted and its practical implementation is discussed. It is shown that the proposed architecture is flexible in terms of implementation and offers a convenient trade-off between capacity and implementation complexity. The difference between achievable capacity in the proposed architecture and theoretical limits is negligible and converges to a constant at high SNR. Simulation results demonstrate that the proposed architecture provides significant performance gain as compared to existing LST architectures and approaches the near optimum bit-interleaved coded modulation (BICM) within a fraction of 1 dB