Abstract

Verification and validation have become very important steps in systems engineering. This is due to the increasing complexity of nowadays systems. Verification and validation aims at detecting flaws early in the design process and/or to verify/validate design models of systems. The state of the art techniques in this field are mainly based on simulation and extensive testing. In this thesis, we propose a new paradigm for verification and validation in systems engineering. It is based on an established synergy between program analysis, software engineering techniques and automatic verification. To illustrate this paradigm, we present a technique for the verification/validation of state-chart diagrams in UML/SysML modeling languages.