Cho, Hansu, Yu, Lochi and Abdi, Samar (2013) Automatic Generation of Transducer Models for Bus-Based MPSoC Design. IEEE Transactions on Computers, 62 (2). pp. 211-224. ISSN 0018-9340
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Official URL: http://dx.doi.org/10.1109/TC.2012.157
Abstract
This paper presents methods for automatic generation of models of Transducer, a highly flexible communication module for interfacing Multiprocessor System-on-Chip (MPSoC) components. We describe the transducer architecture, comprising the bus interface, high-level communication controllers and buffer management blocks. The well-defined architecture of the transducer enables automatic generation of its Transaction-level and Register-transfer level (RTL) models. Moreover, the simple interface of the transducer provides for a well-defined software interface, making it easy to update the software after changes in MPSoC platform. Our experimental results show that MPSoC design for industrial-size applications, such as MP3 decoder and JPEG encoder, greatly benefits from automatic generation of transducer models. We found productivity gains of 9-23× due to significant savings in modeling effort. On the quality axis, we show that MPSoC communication design using automatically generated transducers has very little overhead in communication delay over a fully connected point-to-point communication architecture. Finally, we show that our automatically generated TLMs greatly reduce the system-level modeling time and provide a fast executable model for early functional validation.
| Divisions: | Concordia University > Gina Cody School of Engineering and Computer Science > Electrical and Computer Engineering |
|---|---|
| Item Type: | Article |
| Refereed: | Yes |
| Authors: | Cho, Hansu and Yu, Lochi and Abdi, Samar |
| Journal or Publication: | IEEE Transactions on Computers |
| Date: | 2013 |
| Digital Object Identifier (DOI): | 10.1109/TC.2012.157 |
| Keywords: | Abstracts , Computer architecture , Protocols , Software , Time domain analysis , Time varying systems , Transducers, Multiprocessor System-on-Chip Design , System-level modeling , communication architecture |
| ID Code: | 975144 |
| Deposited By: | Danielle Dennie |
| Deposited On: | 18 Jan 2013 18:24 |
| Last Modified: | 18 Jan 2018 17:39 |
References:
[1] Networks on Chips: Technology and Tools, G. De Micheli and L. Benini, eds. Morgan Kaufmann, 2006.[2] OSCI, http://www.systemc.org, 2012.
[3] TLM 2 white paper, http://www.systemc.org, May 2007.
[4] A. Donlin, “Transaction Level Modeling: Flows and Use Models,”Proc. Second IEEE/ACM/IFIP Int’l Conf. Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 75-80, 2004.
[5] L. Cai and D. Gajski, “Transaction Level Modeling: An Overview,”Proc. First IEEE/ACM/IFIP Int’l Conf. Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 19-24, 2003.
[6] A. Gerstlauer, D. Shin, J. Peng, R. Do¨mer, and D. Gajski, “Automatic, Layer-Based Generation of System-on-Chip Bus Communication Models,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 9, pp. 1676-1687, Sept. 2007.
[7] J. Cornet, F. Maraninchi, and L. Maillet-Contoz, “A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of Systems-on-Chip,” Proc. Conf. Design, Automation and Test in Europe (DATE), pp. 9-14, 2008.
[8] C.K. Lo and R.S. Tsay, “Automatic Generation of Cycle Accurate and Cycle Count Accurate Transaction Level Bus Models from a Formal Model,” Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), pp. 558-563, 2009.
[9] H.W.M. Van Moll, H. Corporaal, V. Reyes, and M. Boonen, “Fast and Accurate Protocol Specific Bus Modeling Using TLM 2.0,” Proc. Design, Automation and Test in Europe Conf., pp. 316-319, 2009.
[10] N. Bombieri, F. Fummi, and V. Guarnieri, “Automatic Synthesis of OSCI TLM-2.0 Models into RTL Bus-Based IPs,” Proc. High Level Design Validation and Test Workshop (HLDVT), pp. 105-112, 2010.
[11] M. Thompson, T. Stefanov, H. Nikolov, A.D. Pimentel, C. Erbas, S. Polstra, and E.F. Deprettere, “A Framework for Rapid System-Level Exploration, Synthesis, and Programming of Multimedia MP-SoCs,” Proc. IEEE/ACM Int’l Conf. Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 9-14, 2007.
[12] J. Gladigau, A. Gerstlauer, C. Haubelt, M. Streubuhr, and J. Teich, “A System-Level Synthesis Approach from Formal Application Models to Generic Bus-Based MPSoCs,” Proc. Int’l Conf. Embedded Computer Systems (SAMOS), pp. 118-125, 2010.
[13] A. Grasset, F. Rousseau, and A.A. Jerraya, “Automatic Generation of Component Wrappers by Composition of Hardware Library Elements Starting from Communication Service Specification,” Proc. IEEE Int’l Workshop Rapid System Prototyping, pp. 47- 53, 2005.
[14] J. Zimmermann, O. Bringmann, A. Braun, and W. Rosenstiel, “Integration of High-Level Synthesis in ESL Platform Modeling by Automated Generation of Protocol Adapters,” Proc. Int’l Conf. Comm., Circuits and Systems, pp. 1149-1154, 2009.
[15] S. Watanabe, K. Seto, Y. Ishikawa, S. Komatsu, and M. Fujita, “Protocol Transducer Synthesis Using Divide and Conquer Approach,” Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), pp. 280-285, 2007.
[16] A. Sangiovanni-Vincentelli, “Quo Vadis SLD: Reasoning about Trends and Challenges of System-Level Design,” Proc. IEEE, vol. 95, no. 3, pp. 467-506, Mar. 2007.
[17] Xilinx, Embedded System Tools Reference Manual, 2005.
[18] H. Cho and S. Abdi, “Automatic Generation of Transducer
Models for Multicore System Design,” Proc. IEEE Int’l High Level Design Validation and Test Workshop (HLDVT), pp. 72-79, 2011.
[19] S. Abdi, G. Schirner, I. Viskic, H. Cho, Y. Hwang, L. Yu, and D. Gajski, “Hardware-Dependent Software Synthesis for Many-Core Embedded Systems,” Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), pp. 304-310, 2009.
[20] S. Abdi, Y. Hwang, L. Yu, G. Schirner, and D. Gajski, “Automatic TLM Generation for Early Validation of Multicore Systems,” IEEE Design and Test of Computers, vol. 28, no. 3, pp. 10-19, May/June 2011.
[21] G.K. Wallace, “The JPEG Still Picture Compression Standard,” Comm. ACM, vol. 34, pp. 30-44, 1991.
[22] ITU-T, ISO/IEC JTC1, “Information Technology - Generic Coding of Moving Pictures and Associated Audio Information,” ITU-T Recommendation ISO/IEC 13818-3, 1998.
[23] Xilinx, MicroBlaze Processor Reference Manual, 2007.
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