Abstract

System-on-chip (SoC) is a major revolution taking place in the design of integrated circuits due to the unprecedented levels of integration possible. To specify, design, and implement complex SoC systems, the need arises to move beyond exist ing register transfer level (RTL) of abstraction. A new modeling method, transaction level modeling (TLM) has been proposed recently to fulfil this need. TLM modules communicate with each other through function calls and allow the designers to focus on the functionality, while abstracting away implementation details. At the RTL, however, different modules communicate through pin level signaling. SoC design methodologies involve the integration of different intellectual property (IP) blocks modeled at different levels of abstraction. Therefore a special module or channel is needed in order to link modules, IPs, designed at different levels of abstraction. This module, called transactor can be modeled using a finite state machine (FSM) providing a functional specification of the protocol's behavior. In this thesis, we propose to specify TLM-RTL transactor behaviors using the Abstract State Machine Language (AsmL). Based on AsmL specification, we have developed a methodology and tool that automatically generates SystemC code for the transactors. SystemC is a system level description language, which became IEEE standard recently. Along with the AsmL specification approach, we also proposed another approach where the transactor behavior can be described by drawing FSMs graphically and the tool will then generate SystemC code from the graphical FSM description automatically. The proposed approaches have been implemented and applied on several case studies including an UTOPIA standard protocol.