Narayanan, Rajeev, Seghair, Ibtissem, Zaki, Mohamed H. and Tahar, Sofiène (2012) Statistical Run-Time Verification of Analog Circuits in Presence of Noise and Process Variation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems . p. 1. ISSN 1063-8210
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Official URL: http://dx.doi.org/10.1109/TVLSI.2012.2219083
Abstract
Noise and process variation present a practical limit on the performance of analog circuits. This paper proposes a methodology for modeling and verification of analog designs in the presence of shot noise, thermal noise, and process variations. The idea is to use stochastic differential equations to model noise in additive and multiplicative form and then combine process variation due to 0.18 μm technology in a statistical run-time verification environment. The efficiency of MonteCarlo and Bootstrap statistical techniques are compared for a Colpitts oscillator and a phase locked loop-based frequency synthesizer circuit.
Divisions: | Concordia University > Gina Cody School of Engineering and Computer Science > Electrical and Computer Engineering |
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Item Type: | Article |
Refereed: | Yes |
Authors: | Narayanan, Rajeev and Seghair, Ibtissem and Zaki, Mohamed H. and Tahar, Sofiène |
Journal or Publication: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Date: | November 2012 |
Digital Object Identifier (DOI): | 10.1109/TVLSI.2012.2219083 |
Keywords: | Analog designs noise process variation run-time verification statistical techniques stochastic differential equations. |
ID Code: | 977358 |
Deposited By: | Danielle Dennie |
Deposited On: | 14 Jun 2013 13:11 |
Last Modified: | 18 Jan 2018 17:44 |
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