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Formal verification of a SONET data stream processor


Formal verification of a SONET data stream processor

Tahar, Sofiène, Zobair, M.H. and Song, X. (2004) Formal verification of a SONET data stream processor. IEE Proceedings - Computers and Digital Techniques, 151 (1). p. 71. ISSN 13502387

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IEECDT-2004.pdf - Accepted Version

Official URL: http://dx.doi.org/10.1049/ip-cdt:20040034


We describe the formal verification of an industrial hardware design from PMC-Sierra, Inc. The design under investigation is a telecom system block, which processes a portion of the synchronous optical network (SONET) line overhead of a received data stream. We adopted a hierarchical modelling and verification approach which follows the natural design hierarchy. The formal specification and verification have been carried out based on multiway decision graphs (MDG), a new decision diagram subsuming the traditional binary decision diagrams and allowing abstract data and functions. The verification has been performed using both equivalence and model checking. To measure the performance of the MDG-based model checking, we also conducted a comparative verification of the same design using Cadence FormalCheck.

Divisions:Concordia University > Gina Cody School of Engineering and Computer Science > Electrical and Computer Engineering
Item Type:Article
Authors:Tahar, Sofiène and Zobair, M.H. and Song, X.
Journal or Publication:IEE Proceedings - Computers and Digital Techniques
Digital Object Identifier (DOI):10.1049/ip-cdt:20040034
Keywords:SONET decision diagrams formal verification hardware description languages
ID Code:977382
Deposited By: Danielle Dennie
Deposited On:14 Jun 2013 16:07
Last Modified:18 Jan 2018 17:44
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