Williams, Christopher (2013) Power and Noise Configurable Phase-Locked Loop Using Multi-Oscillator Feedback Alignment. Masters thesis, Concordia University.
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Abstract
On-the-fly data rate changes allow for the data rate to be lowered when peak speeds are not needed. A PLL is presented that contains a plurality of sub-VCOs, each able to be enabled or disabled. The goal of this technique is having the power dissipation proportional to the data rate, in order to obtain a fixed energy per transmitted bit. The proposed architecture accomplishes data rate changes by quickly reconfiguring itself and exploiting known power / jitter trade offs in circuit design. The proposed architecture can be applied to either electrical or optical serial links that do not contain a forwarded clock.
By relaxing the jitter constraints at lower data rates, the receiver can enter a low-power mode enabling energy savings when maximum data rates are not required. A bank of sub-VCOs is introduced and can be brought up to speed and connected. An activation procedure and compensation methods have also been introduced in order to avoid arbitrary phases during start-up, which would lead to large phase excursions. Simulations show that by enabling the high-performance mode, data rates of 25 Gb/s are able to be obtained in a CDR setting. In the low power mode, the jitter increases by 1.5 times but the power reduces by 46%. In this mode, the architecture can support data rates of 12.5 Gb/s. Therefore, this system responds to the need of improving energy efficiency in receivers by allowing a dynamic reconfiguration of the circuit; varying power in response to jitter specifications.
| Divisions: | Concordia University > Gina Cody School of Engineering and Computer Science > Electrical and Computer Engineering |
|---|---|
| Item Type: | Thesis (Masters) |
| Authors: | Williams, Christopher |
| Institution: | Concordia University |
| Degree Name: | M.A. Sc. |
| Program: | Electrical and Computer Engineering |
| Date: | 30 August 2013 |
| Thesis Supervisor(s): | Cowan, Glenn and Liboiron-Ladouceur, Odile |
| Keywords: | Multi-oscillator, Power configurable VCO, Noise configurable VCO, On-the-fly data rate changes |
| ID Code: | 977748 |
| Deposited By: | CHRISTOPHER WILLIAMS |
| Deposited On: | 18 Nov 2013 16:59 |
| Last Modified: | 18 Jan 2018 17:45 |
References:
[1] T. Toifl, et al., “A 72mW 0.03mm2inductorless 40 Gb/s CDR in 65nmSOI CMOS,” IEEE ISSCC, pp.226 227, Feb. 2007.[2] L. Rodoni, et al., “A 5.75 to 44 Gb/s quarter rate CDR with data rate selection in 90nm bulk CMOS,” IEEE J. Solid-State Circuits, vol. 44,no.7, pp. 1927 1941, Jul. 2009.
[3] M. Mansurl, et al., "A scalable 0.128-to-1 Tb/s 0.8-to-2.6 pJ/b 64-lane parallel I/O in 32 nm CMOS," IEEE ISSCC, pp. 402 - 404, Feb. 2013.
[4] A. Hajimiri, S. Limotyrakis and T. H. Lee, “Jitter and phase noise in ring oscillators,” IEEE J. Solid-State Circuits, vol. 34, no.6, pp. 790 804, Jun. 1999.
[5] M. Behbahani and G. E. R. Cowan, “Phase-Noise tuneable ring voltage-controlled oscillator in 90 nm CMOS,” IEEE MWSCAS 2013, pp.1031 1034, Aug. 2013.
[6] S. Kobayashi and M. Hashimoto, "A multibitrate burst-mode CDR circuit with bit-rate discrimination function from 52 to 1244 Mb/s," IEEE Photonics Technol. Lett., vol. 13, no. 11, Nov. 2001.
[7] B. Razavi, Design of Integrated Circuits for Optical Communications, 2nd ed. New Jersey: Wiley, 2012.
[8] J. P. Hein and J. W. Scott, “z-Domain model for discrete-time PLL’s”, IEEE Trans. Circuits Syst., vol. 35, no. 11, pp. 1393 1400, Nov. 1988.
[9] A. S. Sedra and K. C. Smith, Microelectronic Circuits, 5th ed. New York: Oxford, 2004.
[10] T. Toifl, et al., “A 0.94-ps-RMS-jitter 0.016mm2 2.5GHz multiphase generator PLL with 360o digitally programmable phase shift for10 Gb/s serial links,” IEEE J. Soild-State Circuits, vol. 40, no.12, pp.2700 2712, Dec. 2005.
[11] G. Zhou, “Design of voltage-controlled oscillators based on static-CMOS inverters in 90nm process,” M.S. thesis, ECE, Concordia, Montreal, QC, 2011.
[12] T. C. Carusone, D. A. Johns and K. W. Martin, Analog Integrated Circuit Design, 2nd ed. Wiley, 2012.
[13] C. Williams, G. E. R. Cowan and O. Liboiron-Ladouceur, “Power and noise configurable phase-locked loop using multi-oscillator feedback alignment”, IEEE MWSCAS 2013, pp. 1023 1026, Aug. 2013.
[14] R. E. Best, Phase-Locked Loops: Design, Simulation and Applications, 6thed. New York: McGraw, 2007.
[15] R. C. Dorf, Modern Control Systems, 12thed. New Jersey: Pearson, 2011.
[16] N. Roberts. (2003, Jul. 14) Digital noise and jitter – a primer for digital designers [Online]. Available: http://www.eetimes.com/document.asp?doc_id=1277196
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