Abstract

Information technology, at present has thrived to great aspects and every day more beneficiary of this blessing is being connected to the modern invention and technology. With the swift growth of communication networks, there has been a high demand for efficient and reliable digital transmission and data storage system. LDPC is one of the channel codes for error correcting that have been developed for competent systems that require higher reliability. For low-end devices requiring a limited battery or computational power, low complexity decoders are useful. For LDPC codes, the presence of short cycle in the parity-check matrix lower the decoding threshold making it less efficient. In this research, a method has been developed from an existing algorithm that finds out the exact position of potential bits forming cycle-4 in the parity check matrix that might create decoding failure after transmission in binary erasure channel. Once the short cycles are detected, it can be removed by puncturing method to obtain capacity achieving codes. The code obtained by the method has a threshold 0.42 and rate 0.5, which is asymptotically close to the mother code. Simulations show that for less number of iterations and in the presence of same channel erasure the decoder block error probability close to 10-6 is achievable. As no other additional decoding algorithm is employed, the proposed scheme does not add additional computational complexity to the decoder. Furthermore, as an extension to the method a scheme has been proposed to generate rate-compatible LDPC codes using 0.5 rate regular code with puncturing method varying puncturing fractions. By the proposed method of generating different rate code, same amount of information can be sent with less parity.