Abstract

Due to the radioactive nature of the space environment, the integrated circuits in space suffer from reliability problems. This threat is due to the presence of high energy ionizing particles like cosmic ray neutrons and their interaction with the semiconductor devices. When a high energy particle strikes a transistor, it induces a transient for a short period of time. This transient temporarily changes the output of its respective combinational gate. This phenomenon is called a Single Event Transient (SET). The SET can propagate through the circuit and could potentially get latched in a state element, causing a soft error. It has lately been discovered that the cosmic ray neutrons cause errors even at ground level.

Moreover, due to the rapid advancements in CMOS technology, the size of the semiconductor devices has reduced significantly. With this reduction in the device size, the radiation particles with lesser energies could cause a soft error. At this smaller technology node size, a single high energy particle can induce transients in multiple combinational gates resulting in Single Event Multiple Transients (SEMTs). Furthermore, rapid technology scaling has resulted in frequent SEMTs and infrequent SETs. This conjointly increases the difficulty in the estimation of the Soft Error Rate (SER). Therefore, there is a need for accurate and cost-effective techniques to study and estimate the reliability of the digital circuits.

This thesis presents a new technique to model the effects of SEMTs on digital circuits based on Satisfiability Modulo Theories (SMT). The presented technique considers the layout-based adjacencies as SEMT originating sites and includes the effects of logical, electrical, and temporal masking while propagating the SEMT faults in the circuit. The technique is applied to the ISCAS’85 benchmark circuits and the 32-bit SPARC V8 based processor LEON3. The results show the proposed technique achieves an average speed-up of 12.64 while estimating the SER, when compared to conventional HDL based fault injection simulation techniques.