Yasoubi, Monazzahalsadat (2020) An Efficient Hardware Implementation of LDPC Decoder. Masters thesis, Concordia University.
Preview |
Text (application/pdf)
2MBYasoubi_MSc_S2020.pdf - Accepted Version Available under License Spectrum Terms of Access. |
Abstract
Reliable communication over noisy channel is an old but still challenging issues for communication engineers. Low density parity check codes (LDPC) are linear block codes proposed by Robert G. Gallager in 1960. LDPC codes have lesser complexity compared to Turbo-codes. In most recent wireless communication standard, LDPC is used as one of the most popular forward error correction (FEC) codes due to their excellent error-correcting capability. In this thesis we focus on hardware implementation of the LDPC used in Digital Video Broadcasting - Satellite - Second Generation (DVB-S2) standard ratified in 2005. In architecture design of LDPC decoder, because of the structure of DVB-S2, a memory mapping scheme is used that allows 360 functional units implement simultaneously. The functional units are optimized to reduce hardware resource utilization on an FPGA. A novel design of Range addressable look up table (RALUT) for hyperbolic tangent function is proposed that simplifies the LDPC decoding algorithm while the performance remains the same. Commonly, RALUTs are uniformly distributed on input, however, in our proposed method, instead of representing the LUT input uniformly, we use a non-uniform scale assigning more values to those near zero. Zynq XC7Z030, a family of FPGA’s, is used for Evaluation of the complexity of the proposed design. Synthesizes result show the speed increase due to use of LUT method, however, LUT demand more memory. Thus, we decrease the usage of resource by applying RALUT method.
| Divisions: | Concordia University > Gina Cody School of Engineering and Computer Science > Electrical and Computer Engineering |
|---|---|
| Item Type: | Thesis (Masters) |
| Authors: | Yasoubi, Monazzahalsadat |
| Institution: | Concordia University |
| Degree Name: | M.A. Sc. |
| Program: | Electrical and Computer Engineering |
| Date: | 13 February 2020 |
| Thesis Supervisor(s): | Mohammad Reza, Soleymani |
| Keywords: | LDPC code, DVBS2 standard, Hardware implementation, Vivado HLS. |
| ID Code: | 986490 |
| Deposited By: | Monazzahalsadat Yasoubi |
| Deposited On: | 26 Jun 2020 13:43 |
| Last Modified: | 26 Jun 2020 13:43 |
References:
[1]. R. G. Gallager,“Low density parity check codes,” IRE Trans. Inform. Theory, IT-8: 21-28, January 1962.[2]. R. G. Gallager, Low density parity check codes, MIT press, Cambridge, 1963.
[3] A. Shokrollahi, ,“LDPC codes: An Introduction,“ April, 2003.
[4] D. J. C. MacKay and R. M. Neal, “Near Shannon limit performance of low density parity check codes,” Electron. Lett., vol. 32, pp. 1645–1646, Aug. 1996.
[5] N. Wiberg,“Codes and decoding on general graphs,” Dissertation no. 440, Dept. Elect. Eng. Linkping Univ., Linkping , Sweden, 1996.
[6] M. Luby, M. Mitzenmacher, A. Shokrollahi, D. Spielman, and V. Stemann,“Practical loss-resilient codes,” in Proc. 29th Annual ACM Symp. Theory of Computing, 1997, pp. 150–159.
[7] M. Sipser and D. Spielman, “Expander codes,” IEEE Trans. Inform.Theory, vol. 42, pp. 1710–1722, Nov. 1996.
[8] D. J. C. MacKay, S. T. Wilson, and M. C. Davey, “Comparison of constructions of irregular Gallager codes,” in Proc. 36th Allerton Conf. Communication, Control, and Computing, Sept. 1998.
[9]. El-Sherbini, Ahmed M. "Method and apparatus for differential run-length coding." U.S. Patent No. 4,631,521. 23 Dec. 1986.
[10].S. Lin and D. J. Costello, Error Control Coding: Fundamentals and Applications, 2nd Edition, Prentice-Hall, 2005. Chapter 17.
[11]. T. J. Richardson and R. L. Urbanke, “Efficient encoding of low density parity check codes,” IEEE Trans. Inform. Theory, February 2001.
[12] Cover, Thomas M., and Joy A. Thomas. Elements of information theory. John Wiley & Sons, 2012.
[13] Slepian, David, and Jack Wolf. "Noiseless coding of correlated information sources." IEEE Transactions on information Theory 19.4 (1973): 471-480.
[14] Wyner, Aaron, and Jacob Ziv. "The rate-distortion function for source coding with side information at the decoder." IEEE Transactions on information theory 22.1 (1976): 1-10.
[15] Shamai, Shlomo, and Sergio Verdú. "Capacity of channels with uncoded side information." European Transactions on Telecommunications 6.5 (1995): 587-600.
[16] European Telecommunications Standards Institude (ETSI). Digital Video Broadcasting (DVB) Second generation framing structure for broadband satellite applications; EN 302 307 V1.1.1. www.dvb.org
[17]. Maddah-Ali, Mohammad Ali, and Urs Niesen. "Fundamental limits of caching." IEEE Transactions on Information Theory60.5 (2014): 2856-2867.
[18]. Niesen, Urs, and Mohammad Ali Maddah-Ali. "Coded caching with non-uniform demands." IEEE Transactions on Information Theory 63.2 (2017): 1146-1158.
[19]. M. A. Maddah-Ali and U. Niesen, “Decentralized coded caching attains order-optimal memory-rate tradeoff,” arXiv:1301.5848 [cs.IT], Jan. 2013.
[20]. Pedarsani, Ramtin, Mohammad Ali Maddah-Ali, and Urs Niesen. "Online coded caching." IEEE/ACM Transactions on Networking (TON) 24.2 (2016): 836-845.
[21]. Timo, Roy, et al. "A rate-distortion approach to caching." IEEE transactions on information theory 64.3 (2018): 1957-1976.
[22] C.-Y. Wang, S. H. Lim, and M. Gastpar, “Information-theoretic caching: Sequential coding for computing,” IEEE Trans. Inf. Theory, vol. 62, no. 11, pp. 6393–6406, Nov. 2016.
[23]. Martin, Grant, and Gary Smith. "High-level synthesis: Past, present, and future." IEEE Design & Test of Computers 26.4 (2009): 18-25.
[24]. Casseau, Emmanuel, et al. "C-based rapid prototyping for digital signal processing." 2005 13th European Signal Processing Conference. IEEE, 2005.
[25]. Lai, Yung-Te, Massoud Pedram, and Sarma BK Vrudhula. "BDD based decomposition of logic functions with application to FPGA synthesis." 30th ACM/IEEE Design Automation Conference. IEEE, 1993.
[26]. H. Jin, A. Khandekar, and R. McEliece, "Irregular repeat-accumulate codes," in 2nd International Symposium on Turbo Codes and Related Topics, September 2000.
[27]. ETSI, Digital Video Broadcasting (DVB): Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications (DVB-S2), EN 302 307 V 1.2.1." August 2009.
[28]. ETSI, Digital Video Broadcasting (DVB): User guidelines for the second generation system for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications (DVB-S2), TR 102 376 V 1.1.1." February 2005.
[29]. M. Gomes, G. Falcao, A. Sengo, V. Ferreira, V. Silva, and M. Falcao, High throughput encoder architecture for DVB-S2 LDPC-IRA codes," in International Conference on Microelectronics, 2007. ICM 2007, December 2007, pp. 271{274.
[30]. Loi, Kung Chi Cinnati. Field-programmable Gate-array (FPGA) Implementation of Low-density Parity-check (LDPC) Decoder in Digital Video Broadcasting-Second Generation Satellite (DVB-S2). Diss. University of Saskatchewan, 2010.
[31] Matt Pharr and Randima Fernando. GPU Gems 2: Programming Techniques for High-Performance Graphics and General-Purpose Computation. Addison-Wesley Professional, Boston, MA, USA, 2005.
[32] K. Basterretxea, J. Tarela, and I. D. Campo. Approximation of sigmoid function and the derivative for hardware implementation of arti_cial neurons. IEE Proceedings - Circuits, Devices and Systems, 151(1):18.24, February 2004.
[33] F. Piazza, A. Uncini, and M. Zenobi. Neural networks with digital lut activation functions. IEE Proceedings - Circuits, Devices and Systems, 151(1):18.24, February 2004.
[34] S. Vassiliadis, M. Zhang, and J. Delgado-Frias. Elementary function generators for neural-network emulators. IEEE Transactions on Neural Networks, 11(6):1438.1449, November 2000.
[35]. Leboeuf, Karl, et al. "High speed VLSI implementation of the hyperbolic tangent sigmoid function." 2008 Third International Conference on Convergence and Hybrid Information Technology. Vol. 1. IEEE, 2008.
[36]. Leboeuf, Karl, et al. "High speed VLSI implementation of the hyperbolic tangent sigmoid function." 2008 Third International Conference on Convergence and Hybrid Information Technology. Vol. 1. IEEE, 2008.
[37]. R. Muscedere, V. Dimitrov, G. Jullien, and W. Miller. Efficient techniques for binary-to multi digit multi-dimensional logarithmic number system conversion using range addressable look-up tables. IEEE Transactions on Computers, 54(3):257.271, March 2005.
[38] S. Lin and D. J. C. Jr., Error Control Coding, 2nd ed. Upper Saddle River, NJ, USA: Pearson Prentice Hall, 2004.
[39] https://www.xilinx.com/support/documentation/sw_manuals/ug998-vivado-intro-fpga-design-hls.pdf
[40]. Viterbi, Andrew J., and Jim K. Omura. Principles of digital communication and coding. Courier Corporation, 2013.
[41] R. Gray and A. Wyner, “Source coding for a simple network,” Bell Systems Technical Journal, vol. 53, no. 9, pp. 1681 – 1721, 1974
All items in Spectrum are protected by copyright, with all rights reserved. The use of items is governed by Spectrum's terms of access.
Repository Staff Only: item control page
Download Statistics
Download Statistics